CMSIS2000  0.0.7
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Data Fields
SCB_Type Struct Reference
System Control Block (SCB)

Structure type to access the System Control Block (SCB). More...

#include <core_cm0.h>

Data Fields

__I uint32_t ADR
__IO uint32_t AFSR
__IO uint32_t AIRCR
__IO uint32_t BFAR
__IO uint32_t CCR
__IO uint32_t CFSR
__IO uint32_t CPACR
__I uint32_t CPUID
__I uint32_t DFR
__IO uint32_t DFSR
__IO uint32_t HFSR
__IO uint32_t ICSR
__I uint32_t ISAR [5]
__IO uint32_t MMFAR
__I uint32_t MMFR [4]
__I uint32_t PFR [2]
uint32_t RESERVED0
uint32_t RESERVED1
__IO uint32_t SCR
__IO uint32_t SFCR
__IO uint32_t SHCSR
__IO uint32_t SHP [2]
__IO uint8_t SHP [12]
__IO uint32_t VTOR

Detailed Description

Structure type to access the System Control Block (SCB).

Definition at line 290 of file core_cm0.h.

Field Documentation

__I uint32_t SCB_Type::ADR

Offset: 0x04C (R/ ) Auxiliary Feature Register

Definition at line 331 of file core_cm3.h.

__IO uint32_t SCB_Type::AFSR

Offset: 0x03C (R/W) Auxiliary Fault Status Register

Definition at line 328 of file core_cm3.h.

__IO uint32_t SCB_Type::AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

Definition at line 295 of file core_cm0.h.

__IO uint32_t SCB_Type::BFAR

Offset: 0x038 (R/W) BusFault Address Register

Definition at line 327 of file core_cm3.h.

__IO uint32_t SCB_Type::CCR

Offset: 0x014 (R/W) Configuration Control Register

Definition at line 297 of file core_cm0.h.

__IO uint32_t SCB_Type::CFSR

Offset: 0x028 (R/W) Configurable Fault Status Register

Definition at line 323 of file core_cm3.h.

__IO uint32_t SCB_Type::CPACR

Offset: 0x088 (R/W) Coprocessor Access Control Register

Definition at line 335 of file core_cm3.h.

__I uint32_t SCB_Type::CPUID

Offset: 0x000 (R/ ) CPUID Base Register

Definition at line 292 of file core_cm0.h.

__I uint32_t SCB_Type::DFR

Offset: 0x048 (R/ ) Debug Feature Register

Definition at line 330 of file core_cm3.h.

__IO uint32_t SCB_Type::DFSR

Offset: 0x030 (R/W) Debug Fault Status Register

Definition at line 325 of file core_cm3.h.

__IO uint32_t SCB_Type::HFSR

Offset: 0x02C (R/W) HardFault Status Register

Definition at line 324 of file core_cm3.h.

__IO uint32_t SCB_Type::ICSR

Offset: 0x004 (R/W) Interrupt Control and State Register

Definition at line 293 of file core_cm0.h.

__I uint32_t SCB_Type::ISAR

Offset: 0x060 (R/ ) Instruction Set Attributes Register

Definition at line 333 of file core_cm3.h.

__IO uint32_t SCB_Type::MMFAR

Offset: 0x034 (R/W) MemManage Fault Address Register

Definition at line 326 of file core_cm3.h.

__I uint32_t SCB_Type::MMFR

Offset: 0x050 (R/ ) Memory Model Feature Register

Definition at line 332 of file core_cm3.h.

__I uint32_t SCB_Type::PFR

Offset: 0x040 (R/ ) Processor Feature Register

Definition at line 329 of file core_cm3.h.

uint32_t SCB_Type::RESERVED0

Definition at line 294 of file core_cm0.h.

uint32_t SCB_Type::RESERVED1

Definition at line 298 of file core_cm0.h.

__IO uint32_t SCB_Type::SCR

Offset: 0x010 (R/W) System Control Register

Definition at line 296 of file core_cm0.h.

__IO uint32_t SCB_Type::SFCR

Offset: 0x290 (R/W) Security Features Register

Definition at line 308 of file core_sc000.h.

__IO uint32_t SCB_Type::SHCSR

Offset: 0x024 (R/W) System Handler Control and State Register

Definition at line 300 of file core_cm0.h.

__IO uint8_t SCB_Type::SHP

Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

Definition at line 299 of file core_cm0.h.

__IO uint8_t SCB_Type::SHP[12]

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

Definition at line 321 of file core_cm3.h.

__IO uint32_t SCB_Type::VTOR

Offset: 0x008 (R/W) Vector Table Offset Register

Definition at line 317 of file core_cm3.h.

The documentation for this struct was generated from the following files: