CMSIS2000  0.0.7
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Data Fields
NVIC_Type Struct Reference
Nested Vectored Interrupt Controller (NVIC)

Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...

#include <core_cm0.h>

Data Fields

__IO uint32_t IABR [8]
__IO uint32_t ICER [1]
__IO uint32_t ICPR [1]
__IO uint32_t IP [8]
__IO uint8_t IP [240]
__IO uint32_t ISER [1]
__IO uint32_t ISPR [1]
uint32_t RESERVED0 [31]
uint32_t RESERVED2 [31]
uint32_t RESERVED3 [31]
uint32_t RESERVED4 [64]
uint32_t RESERVED5 [644]
uint32_t RSERVED1 [31]
__O uint32_t STIR

Detailed Description

Structure type to access the Nested Vectored Interrupt Controller (NVIC).

Definition at line 265 of file core_cm0.h.

Field Documentation

__IO uint32_t NVIC_Type::IABR

Offset: 0x200 (R/W) Interrupt Active bit Register

Definition at line 291 of file core_cm3.h.

__IO uint32_t NVIC_Type::ICER

Offset: 0x080 (R/W) Interrupt Clear Enable Register

Definition at line 269 of file core_cm0.h.

__IO uint32_t NVIC_Type::ICPR

Offset: 0x180 (R/W) Interrupt Clear Pending Register

Definition at line 273 of file core_cm0.h.

__IO uint8_t NVIC_Type::IP

Offset: 0x300 (R/W) Interrupt Priority Register

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 276 of file core_cm0.h.

__IO uint8_t NVIC_Type::IP[240]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 293 of file core_cm3.h.

__IO uint32_t NVIC_Type::ISER

Offset: 0x000 (R/W) Interrupt Set Enable Register

Definition at line 267 of file core_cm0.h.

__IO uint32_t NVIC_Type::ISPR

Offset: 0x100 (R/W) Interrupt Set Pending Register

Definition at line 271 of file core_cm0.h.

uint32_t NVIC_Type::RESERVED0

Definition at line 268 of file core_cm0.h.

uint32_t NVIC_Type::RESERVED2

Definition at line 272 of file core_cm0.h.

uint32_t NVIC_Type::RESERVED3

Definition at line 274 of file core_cm0.h.

uint32_t NVIC_Type::RESERVED4

Definition at line 275 of file core_cm0.h.

uint32_t NVIC_Type::RESERVED5

Definition at line 294 of file core_cm3.h.

uint32_t NVIC_Type::RSERVED1

Definition at line 270 of file core_cm0.h.

__O uint32_t NVIC_Type::STIR

Offset: 0xE00 ( /W) Software Trigger Interrupt Register

Definition at line 295 of file core_cm3.h.

The documentation for this struct was generated from the following files: