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core_cm0.h
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1 /**************************************************************************//**
2  * @file core_cm0.h
3  * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
4  * @version V3.01
5  * @date 13. March 2012
6  *
7  * @note
8  * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9  *
10  * @par
11  * ARM Limited (ARM) is supplying this software for use with Cortex-M
12  * processor based microcontrollers. This file can be freely distributed
13  * within development tools that are supporting such ARM based processors.
14  *
15  * @par
16  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21  *
22  ******************************************************************************/
23 #if defined ( __ICCARM__ )
24  #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 #ifndef __CORE_CM0_H_GENERIC
32 #define __CORE_CM0_H_GENERIC
33 
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35  CMSIS violates the following MISRA-C:2004 rules:
36 
37  \li Required Rule 8.5, object/function definition in header file.<br>
38  Function definitions in header files are used to allow 'inlining'.
39 
40  \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41  Unions are used for effective representation of core registers.
42 
43  \li Advisory Rule 19.7, Function-like macro defined.<br>
44  Function-like macros are used to allow more efficient code.
45  */
46 
47 
48 /*******************************************************************************
49  * CMSIS definitions
50  ******************************************************************************/
51 /** \ingroup Cortex_M0
52  @{
53  */
54 
55 /* CMSIS CM0 definitions */
56 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
58 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
59  __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
60 
61 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
62 
63 
64 #if defined ( __CC_ARM )
65  #define __ASM __asm /*!< asm keyword for ARM Compiler */
66  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67  #define __STATIC_INLINE static __inline
68 
69 #elif defined ( __ICCARM__ )
70  #define __ASM __asm /*!< asm keyword for IAR Compiler */
71  #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72  #define __STATIC_INLINE static inline
73 
74 #elif defined ( __GNUC__ )
75  #define __ASM __asm /*!< asm keyword for GNU Compiler */
76  #define __INLINE inline /*!< inline keyword for GNU Compiler */
77  #define __STATIC_INLINE static inline
78 
79 #elif defined ( __TASKING__ )
80  #define __ASM __asm /*!< asm keyword for TASKING Compiler */
81  #define __INLINE inline /*!< inline keyword for TASKING Compiler */
82  #define __STATIC_INLINE static inline
83 
84 #endif
85 
86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
87 */
88 #define __FPU_USED 0
89 
90 #if defined ( __CC_ARM )
91  #if defined __TARGET_FPU_VFP
92  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93  #endif
94 
95 #elif defined ( __ICCARM__ )
96  #if defined __ARMVFP__
97  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98  #endif
99 
100 #elif defined ( __GNUC__ )
101  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103  #endif
104 
105 #elif defined ( __TASKING__ )
106  #if defined __FPU_VFP__
107  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108  #endif
109 #endif
110 
111 #include <stdint.h> /* standard types definitions */
112 #include <core_cmInstr.h> /* Core Instruction Access */
113 #include <core_cmFunc.h> /* Core Function Access */
114 
115 #endif /* __CORE_CM0_H_GENERIC */
116 
117 #ifndef __CMSIS_GENERIC
118 
119 #ifndef __CORE_CM0_H_DEPENDANT
120 #define __CORE_CM0_H_DEPENDANT
121 
122 /* check device defines and use defaults */
123 #if defined __CHECK_DEVICE_DEFINES
124  #ifndef __CM0_REV
125  #define __CM0_REV 0x0000
126  #warning "__CM0_REV not defined in device header file; using default!"
127  #endif
128 
129  #ifndef __NVIC_PRIO_BITS
130  #define __NVIC_PRIO_BITS 2
131  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
132  #endif
133 
134  #ifndef __Vendor_SysTickConfig
135  #define __Vendor_SysTickConfig 0
136  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
137  #endif
138 #endif
139 
140 /* IO definitions (access restrictions to peripheral registers) */
141 /**
142  \defgroup CMSIS_glob_defs CMSIS Global Defines
143 
144  <strong>IO Type Qualifiers</strong> are used
145  \li to specify the access to peripheral variables.
146  \li for automatic generation of peripheral register debug information.
147 */
148 #ifdef __cplusplus
149  #define __I volatile /*!< Defines 'read only' permissions */
150 #else
151  #define __I volatile const /*!< Defines 'read only' permissions */
152 #endif
153 #define __O volatile /*!< Defines 'write only' permissions */
154 #define __IO volatile /*!< Defines 'read / write' permissions */
155 
156 /*@} end of group Cortex_M0 */
157 
158 
159 
160 /*******************************************************************************
161  * Register Abstraction
162  Core Register contain:
163  - Core Register
164  - Core NVIC Register
165  - Core SCB Register
166  - Core SysTick Register
167  ******************************************************************************/
168 /** \defgroup CMSIS_core_register Defines and Type Definitions
169  \brief Type definitions and defines for Cortex-M processor based devices.
170 */
171 
172 /** \ingroup CMSIS_core_register
173  \defgroup CMSIS_CORE Status and Control Registers
174  \brief Core Register type definitions.
175  @{
176  */
177 
178 /** \brief Union type to access the Application Program Status Register (APSR).
179  */
180 typedef union
181 {
182  struct
183  {
184 #if (__CORTEX_M != 0x04)
185  uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
186 #else
187  uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
188  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
189  uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
190 #endif
191  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
192  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
193  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
194  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
195  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
196  } b; /*!< Structure used for bit access */
197  uint32_t w; /*!< Type used for word access */
198 } APSR_Type;
199 
200 
201 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
202  */
203 typedef union
204 {
205  struct
206  {
207  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
208  uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
209  } b; /*!< Structure used for bit access */
210  uint32_t w; /*!< Type used for word access */
211 } IPSR_Type;
212 
213 
214 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
215  */
216 typedef union
217 {
218  struct
219  {
220  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
221 #if (__CORTEX_M != 0x04)
222  uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
223 #else
224  uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
225  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
226  uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
227 #endif
228  uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
229  uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
230  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
231  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
232  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
233  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
234  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
235  } b; /*!< Structure used for bit access */
236  uint32_t w; /*!< Type used for word access */
237 } xPSR_Type;
238 
239 
240 /** \brief Union type to access the Control Registers (CONTROL).
241  */
242 typedef union
243 {
244  struct
245  {
246  uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
247  uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
248  uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
249  uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
250  } b; /*!< Structure used for bit access */
251  uint32_t w; /*!< Type used for word access */
252 } CONTROL_Type;
253 
254 /*@} end of group CMSIS_CORE */
255 
256 
257 /** \ingroup CMSIS_core_register
258  \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
259  \brief Type definitions for the NVIC Registers
260  @{
261  */
262 
263 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
264  */
265 typedef struct
266 {
267  __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
268  uint32_t RESERVED0[31];
269  __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
270  uint32_t RSERVED1[31];
271  __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
272  uint32_t RESERVED2[31];
273  __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
274  uint32_t RESERVED3[31];
275  uint32_t RESERVED4[64];
276  __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
277 } NVIC_Type;
278 
279 /*@} end of group CMSIS_NVIC */
280 
281 
282 /** \ingroup CMSIS_core_register
283  \defgroup CMSIS_SCB System Control Block (SCB)
284  \brief Type definitions for the System Control Block Registers
285  @{
286  */
287 
288 /** \brief Structure type to access the System Control Block (SCB).
289  */
290 typedef struct
291 {
292  __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
293  __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
294  uint32_t RESERVED0;
295  __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
296  __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
297  __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
298  uint32_t RESERVED1;
299  __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
300  __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
301 } SCB_Type;
302 
303 /* SCB CPUID Register Definitions */
304 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
305 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
306 
307 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
308 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
309 
310 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
311 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
312 
313 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
314 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
315 
316 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
317 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
318 
319 /* SCB Interrupt Control State Register Definitions */
320 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
321 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
322 
323 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
324 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
325 
326 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
327 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
328 
329 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
330 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
331 
332 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
333 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
334 
335 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
336 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
337 
338 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
339 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
340 
341 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
342 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
343 
344 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
345 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
346 
347 /* SCB Application Interrupt and Reset Control Register Definitions */
348 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
349 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
350 
351 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
352 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
353 
354 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
355 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
356 
357 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
358 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
359 
360 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
361 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
362 
363 /* SCB System Control Register Definitions */
364 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
365 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
366 
367 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
368 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
369 
370 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
371 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
372 
373 /* SCB Configuration Control Register Definitions */
374 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
375 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
376 
377 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
378 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
379 
380 /* SCB System Handler Control and State Register Definitions */
381 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
382 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
383 
384 /*@} end of group CMSIS_SCB */
385 
386 
387 /** \ingroup CMSIS_core_register
388  \defgroup CMSIS_SysTick System Tick Timer (SysTick)
389  \brief Type definitions for the System Timer Registers.
390  @{
391  */
392 
393 /** \brief Structure type to access the System Timer (SysTick).
394  */
395 typedef struct
396 {
397  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
398  __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
399  __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
400  __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
401 } SysTick_Type;
402 
403 /* SysTick Control / Status Register Definitions */
404 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
405 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
406 
407 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
408 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
409 
410 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
411 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
412 
413 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
414 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
415 
416 /* SysTick Reload Register Definitions */
417 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
418 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
419 
420 /* SysTick Current Register Definitions */
421 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
422 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
423 
424 /* SysTick Calibration Register Definitions */
425 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
426 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
427 
428 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
429 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
430 
431 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
432 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
433 
434 /*@} end of group CMSIS_SysTick */
435 
436 
437 /** \ingroup CMSIS_core_register
438  \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
439  \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
440  are only accessible over DAP and not via processor. Therefore
441  they are not covered by the Cortex-M0 header file.
442  @{
443  */
444 /*@} end of group CMSIS_CoreDebug */
445 
446 
447 /** \ingroup CMSIS_core_register
448  \defgroup CMSIS_core_base Core Definitions
449  \brief Definitions for base addresses, unions, and structures.
450  @{
451  */
452 
453 /* Memory mapping of Cortex-M0 Hardware */
454 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
455 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
456 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
457 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
458 
459 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
460 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
461 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
462 
463 
464 /*@} */
465 
466 
467 
468 /*******************************************************************************
469  * Hardware Abstraction Layer
470  Core Function Interface contains:
471  - Core NVIC Functions
472  - Core SysTick Functions
473  - Core Register Access Functions
474  ******************************************************************************/
475 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
476 */
477 
478 
479 
480 /* ########################## NVIC functions #################################### */
481 /** \ingroup CMSIS_Core_FunctionInterface
482  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
483  \brief Functions that manage interrupts and exceptions via the NVIC.
484  @{
485  */
486 
487 /* Interrupt Priorities are WORD accessible only under ARMv6M */
488 /* The following MACROS handle generation of the register offset and byte masks */
489 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
490 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
491 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
492 
493 
494 /** \brief Enable External Interrupt
495 
496  The function enables a device-specific interrupt in the NVIC interrupt controller.
497 
498  \param [in] IRQn External interrupt number. Value cannot be negative.
499  */
500 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
501 {
502  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
503 }
504 
505 
506 /** \brief Disable External Interrupt
507 
508  The function disables a device-specific interrupt in the NVIC interrupt controller.
509 
510  \param [in] IRQn External interrupt number. Value cannot be negative.
511  */
512 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
513 {
514  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
515 }
516 
517 
518 /** \brief Get Pending Interrupt
519 
520  The function reads the pending register in the NVIC and returns the pending bit
521  for the specified interrupt.
522 
523  \param [in] IRQn Interrupt number.
524 
525  \return 0 Interrupt status is not pending.
526  \return 1 Interrupt status is pending.
527  */
528 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
529 {
530  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
531 }
532 
533 
534 /** \brief Set Pending Interrupt
535 
536  The function sets the pending bit of an external interrupt.
537 
538  \param [in] IRQn Interrupt number. Value cannot be negative.
539  */
540 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
541 {
542  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
543 }
544 
545 
546 /** \brief Clear Pending Interrupt
547 
548  The function clears the pending bit of an external interrupt.
549 
550  \param [in] IRQn External interrupt number. Value cannot be negative.
551  */
552 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
553 {
554  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
555 }
556 
557 
558 /** \brief Set Interrupt Priority
559 
560  The function sets the priority of an interrupt.
561 
562  \note The priority cannot be set for every core interrupt.
563 
564  \param [in] IRQn Interrupt number.
565  \param [in] priority Priority to set.
566  */
567 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
568 {
569  if(IRQn < 0) {
570  SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
571  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
572  else {
573  NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
574  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
575 }
576 
577 
578 /** \brief Get Interrupt Priority
579 
580  The function reads the priority of an interrupt. The interrupt
581  number can be positive to specify an external (device specific)
582  interrupt, or negative to specify an internal (core) interrupt.
583 
584 
585  \param [in] IRQn Interrupt number.
586  \return Interrupt Priority. Value is aligned automatically to the implemented
587  priority bits of the microcontroller.
588  */
589 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
590 {
591 
592  if(IRQn < 0) {
593  return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
594  else {
595  return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
596 }
597 
598 
599 /** \brief System Reset
600 
601  The function initiates a system reset request to reset the MCU.
602  */
603 __STATIC_INLINE void NVIC_SystemReset(void)
604 {
605  __DSB(); /* Ensure all outstanding memory accesses included
606  buffered write are completed before reset */
607  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
608  SCB_AIRCR_SYSRESETREQ_Msk);
609  __DSB(); /* Ensure completion of memory access */
610  while(1); /* wait until reset */
611 }
612 
613 /*@} end of CMSIS_Core_NVICFunctions */
614 
615 
616 
617 /* ################################## SysTick function ############################################ */
618 /** \ingroup CMSIS_Core_FunctionInterface
619  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
620  \brief Functions that configure the System.
621  @{
622  */
623 
624 #if (__Vendor_SysTickConfig == 0)
625 
626 /** \brief System Tick Configuration
627 
628  The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
629  Counter is in free running mode to generate periodic interrupts.
630 
631  \param [in] ticks Number of ticks between two interrupts.
632 
633  \return 0 Function succeeded.
634  \return 1 Function failed.
635 
636  \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
637  function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
638  must contain a vendor-specific implementation of this function.
639 
640  */
641 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
642 {
643  if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
644 
645  SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
646  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
647  SysTick->VAL = 0; /* Load the SysTick Counter Value */
648  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
649  SysTick_CTRL_TICKINT_Msk |
650  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
651  return (0); /* Function successful */
652 }
653 
654 #endif
655 
656 /*@} end of CMSIS_Core_SysTickFunctions */
657 
658 
659 
660 
661 #endif /* __CORE_CM0_H_DEPENDANT */
662 
663 #endif /* __CMSIS_GENERIC */
664 
665 #ifdef __cplusplus
666 }
667 #endif