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Data Fields
ITM_Type Struct Reference
Instrumentation Trace Macrocell (ITM)

Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...

#include <core_cm3.h>

Data Fields

__I uint32_t CID0
__I uint32_t CID1
__I uint32_t CID2
__I uint32_t CID3
__IO uint32_t IMCR
__I uint32_t IRR
__O uint32_t IWR
__O uint32_t LAR
__I uint32_t LSR
__I uint32_t PID0
__I uint32_t PID1
__I uint32_t PID2
__I uint32_t PID3
__I uint32_t PID4
__I uint32_t PID5
__I uint32_t PID6
__I uint32_t PID7
union {
   __O uint16_t   u16
   __O uint32_t   u32
   __O uint8_t   u8
} PORT [32]
union {
   __O uint16_t   u16
   __O uint32_t   u32
   __O uint8_t   u8
} PORT [32]
union {
   __O uint16_t   u16
   __O uint32_t   u32
   __O uint8_t   u8
} PORT [32]
uint32_t RESERVED0 [864]
uint32_t RESERVED1 [15]
uint32_t RESERVED2 [15]
uint32_t RESERVED3 [29]
uint32_t RESERVED4 [43]
uint32_t RESERVED5 [6]
__IO uint32_t TCR
__IO uint32_t TER
__IO uint32_t TPR

Detailed Description

Structure type to access the Instrumentation Trace Macrocell Register (ITM).

Definition at line 625 of file core_cm3.h.

Field Documentation

__I uint32_t ITM_Type::CID0

Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

Definition at line 655 of file core_cm3.h.

__I uint32_t ITM_Type::CID1

Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

Definition at line 656 of file core_cm3.h.

__I uint32_t ITM_Type::CID2

Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

Definition at line 657 of file core_cm3.h.

__I uint32_t ITM_Type::CID3

Offset: 0xFFC (R/ ) ITM Component Identification Register #3

Definition at line 658 of file core_cm3.h.

__IO uint32_t ITM_Type::IMCR

Offset: 0xF00 (R/W) ITM Integration Mode Control Register

Definition at line 642 of file core_cm3.h.

__I uint32_t ITM_Type::IRR

Offset: 0xEFC (R/ ) ITM Integration Read Register

Definition at line 641 of file core_cm3.h.

__O uint32_t ITM_Type::IWR

Offset: 0xEF8 ( /W) ITM Integration Write Register

Definition at line 640 of file core_cm3.h.

__O uint32_t ITM_Type::LAR

Offset: 0xFB0 ( /W) ITM Lock Access Register

Definition at line 644 of file core_cm3.h.

__I uint32_t ITM_Type::LSR

Offset: 0xFB4 (R/ ) ITM Lock Status Register

Definition at line 645 of file core_cm3.h.

__I uint32_t ITM_Type::PID0

Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

Definition at line 651 of file core_cm3.h.

__I uint32_t ITM_Type::PID1

Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

Definition at line 652 of file core_cm3.h.

__I uint32_t ITM_Type::PID2

Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

Definition at line 653 of file core_cm3.h.

__I uint32_t ITM_Type::PID3

Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

Definition at line 654 of file core_cm3.h.

__I uint32_t ITM_Type::PID4

Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

Definition at line 647 of file core_cm3.h.

__I uint32_t ITM_Type::PID5

Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

Definition at line 648 of file core_cm3.h.

__I uint32_t ITM_Type::PID6

Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

Definition at line 649 of file core_cm3.h.

__I uint32_t ITM_Type::PID7

Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

Definition at line 650 of file core_cm3.h.

__O { ... } ITM_Type::PORT[32]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

__O { ... } ITM_Type::PORT[32]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

__O { ... } ITM_Type::PORT[32]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

uint32_t ITM_Type::RESERVED0

Definition at line 633 of file core_cm3.h.

uint32_t ITM_Type::RESERVED1

Definition at line 635 of file core_cm3.h.

uint32_t ITM_Type::RESERVED2

Definition at line 637 of file core_cm3.h.

uint32_t ITM_Type::RESERVED3

Definition at line 639 of file core_cm3.h.

uint32_t ITM_Type::RESERVED4

Definition at line 643 of file core_cm3.h.

uint32_t ITM_Type::RESERVED5

Definition at line 646 of file core_cm3.h.

__IO uint32_t ITM_Type::TCR

Offset: 0xE80 (R/W) ITM Trace Control Register

Definition at line 638 of file core_cm3.h.

__IO uint32_t ITM_Type::TER

Offset: 0xE00 (R/W) ITM Trace Enable Register

Definition at line 634 of file core_cm3.h.

__IO uint32_t ITM_Type::TPR

Offset: 0xE40 (R/W) ITM Trace Privilege Register

Definition at line 636 of file core_cm3.h.

__O uint16_t ITM_Type::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

Definition at line 630 of file core_cm3.h.

__O uint32_t ITM_Type::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

Definition at line 631 of file core_cm3.h.

__O uint8_t ITM_Type::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

Definition at line 629 of file core_cm3.h.

The documentation for this struct was generated from the following files: