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core_cm4.h
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1 /**************************************************************************//**
2  * @file core_cm4.h
3  * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4  * @version V3.01
5  * @date 22. March 2012
6  *
7  * @note
8  * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9  *
10  * @par
11  * ARM Limited (ARM) is supplying this software for use with Cortex-M
12  * processor based microcontrollers. This file can be freely distributed
13  * within development tools that are supporting such ARM based processors.
14  *
15  * @par
16  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21  *
22  ******************************************************************************/
23 #if defined ( __ICCARM__ )
24  #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 #ifndef __CORE_CM4_H_GENERIC
32 #define __CORE_CM4_H_GENERIC
33 
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35  CMSIS violates the following MISRA-C:2004 rules:
36 
37  \li Required Rule 8.5, object/function definition in header file.<br>
38  Function definitions in header files are used to allow 'inlining'.
39 
40  \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41  Unions are used for effective representation of core registers.
42 
43  \li Advisory Rule 19.7, Function-like macro defined.<br>
44  Function-like macros are used to allow more efficient code.
45  */
46 
47 
48 /*******************************************************************************
49  * CMSIS definitions
50  ******************************************************************************/
51 /** \ingroup Cortex_M4
52  @{
53  */
54 
55 /* CMSIS CM4 definitions */
56 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
58 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
59  __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
60 
61 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
62 
63 
64 #if defined ( __CC_ARM )
65  #define __ASM __asm /*!< asm keyword for ARM Compiler */
66  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67  #define __STATIC_INLINE static __inline
68 
69 #elif defined ( __ICCARM__ )
70  #define __ASM __asm /*!< asm keyword for IAR Compiler */
71  #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72  #define __STATIC_INLINE static inline
73 
74 #elif defined ( __TMS470__ )
75  #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
76  #define __STATIC_INLINE static inline
77 
78 #elif defined ( __GNUC__ )
79  #define __ASM __asm /*!< asm keyword for GNU Compiler */
80  #define __INLINE inline /*!< inline keyword for GNU Compiler */
81  #define __STATIC_INLINE static inline
82 
83 #elif defined ( __TASKING__ )
84  #define __ASM __asm /*!< asm keyword for TASKING Compiler */
85  #define __INLINE inline /*!< inline keyword for TASKING Compiler */
86  #define __STATIC_INLINE static inline
87 
88 #endif
89 
90 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
91 */
92 #if defined ( __CC_ARM )
93  #if defined __TARGET_FPU_VFP
94  #if (__FPU_PRESENT == 1)
95  #define __FPU_USED 1
96  #else
97  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98  #define __FPU_USED 0
99  #endif
100  #else
101  #define __FPU_USED 0
102  #endif
103 
104 #elif defined ( __ICCARM__ )
105  #if defined __ARMVFP__
106  #if (__FPU_PRESENT == 1)
107  #define __FPU_USED 1
108  #else
109  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
110  #define __FPU_USED 0
111  #endif
112  #else
113  #define __FPU_USED 0
114  #endif
115 
116 #elif defined ( __TMS470__ )
117  #if defined __TI_VFP_SUPPORT__
118  #if (__FPU_PRESENT == 1)
119  #define __FPU_USED 1
120  #else
121  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
122  #define __FPU_USED 0
123  #endif
124  #else
125  #define __FPU_USED 0
126  #endif
127 
128 #elif defined ( __GNUC__ )
129  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
130  #if (__FPU_PRESENT == 1)
131  #define __FPU_USED 1
132  #else
133  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134  #define __FPU_USED 0
135  #endif
136  #else
137  #define __FPU_USED 0
138  #endif
139 
140 #elif defined ( __TASKING__ )
141  #if defined __FPU_VFP__
142  #if (__FPU_PRESENT == 1)
143  #define __FPU_USED 1
144  #else
145  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
146  #define __FPU_USED 0
147  #endif
148  #else
149  #define __FPU_USED 0
150  #endif
151 #endif
152 
153 #include <stdint.h> /* standard types definitions */
154 #include <core_cmInstr.h> /* Core Instruction Access */
155 #include <core_cmFunc.h> /* Core Function Access */
156 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
157 
158 #endif /* __CORE_CM4_H_GENERIC */
159 
160 #ifndef __CMSIS_GENERIC
161 
162 #ifndef __CORE_CM4_H_DEPENDANT
163 #define __CORE_CM4_H_DEPENDANT
164 
165 /* check device defines and use defaults */
166 #if defined __CHECK_DEVICE_DEFINES
167  #ifndef __CM4_REV
168  #define __CM4_REV 0x0000
169  #warning "__CM4_REV not defined in device header file; using default!"
170  #endif
171 
172  #ifndef __FPU_PRESENT
173  #define __FPU_PRESENT 0
174  #warning "__FPU_PRESENT not defined in device header file; using default!"
175  #endif
176 
177  #ifndef __MPU_PRESENT
178  #define __MPU_PRESENT 0
179  #warning "__MPU_PRESENT not defined in device header file; using default!"
180  #endif
181 
182  #ifndef __NVIC_PRIO_BITS
183  #define __NVIC_PRIO_BITS 4
184  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
185  #endif
186 
187  #ifndef __Vendor_SysTickConfig
188  #define __Vendor_SysTickConfig 0
189  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
190  #endif
191 #endif
192 
193 /* IO definitions (access restrictions to peripheral registers) */
194 /**
195  \defgroup CMSIS_glob_defs CMSIS Global Defines
196 
197  <strong>IO Type Qualifiers</strong> are used
198  \li to specify the access to peripheral variables.
199  \li for automatic generation of peripheral register debug information.
200 */
201 #ifdef __cplusplus
202  #define __I volatile /*!< Defines 'read only' permissions */
203 #else
204  #define __I volatile const /*!< Defines 'read only' permissions */
205 #endif
206 #define __O volatile /*!< Defines 'write only' permissions */
207 #define __IO volatile /*!< Defines 'read / write' permissions */
208 
209 /*@} end of group Cortex_M4 */
210 
211 
212 
213 /*******************************************************************************
214  * Register Abstraction
215  Core Register contain:
216  - Core Register
217  - Core NVIC Register
218  - Core SCB Register
219  - Core SysTick Register
220  - Core Debug Register
221  - Core MPU Register
222  - Core FPU Register
223  ******************************************************************************/
224 /** \defgroup CMSIS_core_register Defines and Type Definitions
225  \brief Type definitions and defines for Cortex-M processor based devices.
226 */
227 
228 /** \ingroup CMSIS_core_register
229  \defgroup CMSIS_CORE Status and Control Registers
230  \brief Core Register type definitions.
231  @{
232  */
233 
234 /** \brief Union type to access the Application Program Status Register (APSR).
235  */
236 typedef union
237 {
238  struct
239  {
240 #if (__CORTEX_M != 0x04)
241  uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
242 #else
243  uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
244  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
245  uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
246 #endif
247  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
248  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
249  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
250  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
251  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
252  } b; /*!< Structure used for bit access */
253  uint32_t w; /*!< Type used for word access */
254 } APSR_Type;
255 
256 
257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
258  */
259 typedef union
260 {
261  struct
262  {
263  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
264  uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
265  } b; /*!< Structure used for bit access */
266  uint32_t w; /*!< Type used for word access */
267 } IPSR_Type;
268 
269 
270 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
271  */
272 typedef union
273 {
274  struct
275  {
276  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
277 #if (__CORTEX_M != 0x04)
278  uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
279 #else
280  uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
281  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
282  uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
283 #endif
284  uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
285  uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
286  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
287  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
288  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
289  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
290  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
291  } b; /*!< Structure used for bit access */
292  uint32_t w; /*!< Type used for word access */
293 } xPSR_Type;
294 
295 
296 /** \brief Union type to access the Control Registers (CONTROL).
297  */
298 typedef union
299 {
300  struct
301  {
302  uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
303  uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
304  uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
305  uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
306  } b; /*!< Structure used for bit access */
307  uint32_t w; /*!< Type used for word access */
308 } CONTROL_Type;
309 
310 /*@} end of group CMSIS_CORE */
311 
312 
313 /** \ingroup CMSIS_core_register
314  \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
315  \brief Type definitions for the NVIC Registers
316  @{
317  */
318 
319 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
320  */
321 typedef struct
322 {
323  __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
324  uint32_t RESERVED0[24];
325  __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
326  uint32_t RSERVED1[24];
327  __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
328  uint32_t RESERVED2[24];
329  __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
330  uint32_t RESERVED3[24];
331  __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
332  uint32_t RESERVED4[56];
333  __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
334  uint32_t RESERVED5[644];
335  __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
336 } NVIC_Type;
337 
338 /* Software Triggered Interrupt Register Definitions */
339 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
340 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
341 
342 /*@} end of group CMSIS_NVIC */
343 
344 
345 /** \ingroup CMSIS_core_register
346  \defgroup CMSIS_SCB System Control Block (SCB)
347  \brief Type definitions for the System Control Block Registers
348  @{
349  */
350 
351 /** \brief Structure type to access the System Control Block (SCB).
352  */
353 typedef struct
354 {
355  __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
356  __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
357  __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
358  __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
359  __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
360  __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
361  __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
362  __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
363  __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
364  __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
365  __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
366  __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
367  __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
368  __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
369  __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
370  __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
371  __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
372  __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
373  __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
374  uint32_t RESERVED0[5];
375  __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
376 } SCB_Type;
377 
378 /* SCB CPUID Register Definitions */
379 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
380 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
381 
382 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
383 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
384 
385 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
386 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
387 
388 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
389 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
390 
391 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
392 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
393 
394 /* SCB Interrupt Control State Register Definitions */
395 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
396 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
397 
398 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
399 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
400 
401 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
402 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
403 
404 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
405 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
406 
407 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
408 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
409 
410 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
411 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
412 
413 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
414 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
415 
416 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
417 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
418 
419 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
420 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
421 
422 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
423 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
424 
425 /* SCB Vector Table Offset Register Definitions */
426 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
427 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
428 
429 /* SCB Application Interrupt and Reset Control Register Definitions */
430 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
431 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
432 
433 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
434 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
435 
436 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
437 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
438 
439 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
440 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
441 
442 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
443 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
444 
445 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
446 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
447 
448 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
449 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
450 
451 /* SCB System Control Register Definitions */
452 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
453 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
454 
455 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
456 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
457 
458 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
459 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
460 
461 /* SCB Configuration Control Register Definitions */
462 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
463 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
464 
465 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
466 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
467 
468 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
469 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
470 
471 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
472 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
473 
474 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
475 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
476 
477 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
478 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
479 
480 /* SCB System Handler Control and State Register Definitions */
481 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
482 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
483 
484 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
485 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
486 
487 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
488 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
489 
490 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
491 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
492 
493 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
494 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
495 
496 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
497 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
498 
499 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
500 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
501 
502 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
503 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
504 
505 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
506 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
507 
508 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
509 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
510 
511 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
512 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
513 
514 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
515 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
516 
517 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
518 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
519 
520 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
521 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
522 
523 /* SCB Configurable Fault Status Registers Definitions */
524 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
525 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
526 
527 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
528 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
529 
530 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
531 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
532 
533 /* SCB Hard Fault Status Registers Definitions */
534 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
535 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
536 
537 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
538 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
539 
540 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
541 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
542 
543 /* SCB Debug Fault Status Register Definitions */
544 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
545 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
546 
547 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
548 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
549 
550 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
551 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
552 
553 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
554 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
555 
556 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
557 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
558 
559 /*@} end of group CMSIS_SCB */
560 
561 
562 /** \ingroup CMSIS_core_register
563  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
564  \brief Type definitions for the System Control and ID Register not in the SCB
565  @{
566  */
567 
568 /** \brief Structure type to access the System Control and ID Register not in the SCB.
569  */
570 typedef struct
571 {
572  uint32_t RESERVED0[1];
573  __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
574  __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
575 } SCnSCB_Type;
576 
577 /* Interrupt Controller Type Register Definitions */
578 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
579 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
580 
581 /* Auxiliary Control Register Definitions */
582 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
583 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
584 
585 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
586 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
587 
588 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
589 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
590 
591 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
592 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
593 
594 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
595 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
596 
597 /*@} end of group CMSIS_SCnotSCB */
598 
599 
600 /** \ingroup CMSIS_core_register
601  \defgroup CMSIS_SysTick System Tick Timer (SysTick)
602  \brief Type definitions for the System Timer Registers.
603  @{
604  */
605 
606 /** \brief Structure type to access the System Timer (SysTick).
607  */
608 typedef struct
609 {
610  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
611  __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
612  __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
613  __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
614 } SysTick_Type;
615 
616 /* SysTick Control / Status Register Definitions */
617 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
618 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
619 
620 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
621 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
622 
623 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
624 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
625 
626 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
627 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
628 
629 /* SysTick Reload Register Definitions */
630 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
631 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
632 
633 /* SysTick Current Register Definitions */
634 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
635 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
636 
637 /* SysTick Calibration Register Definitions */
638 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
639 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
640 
641 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
642 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
643 
644 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
645 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
646 
647 /*@} end of group CMSIS_SysTick */
648 
649 
650 /** \ingroup CMSIS_core_register
651  \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
652  \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
653  @{
654  */
655 
656 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
657  */
658 typedef struct
659 {
660  __O union
661  {
662  __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
663  __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
664  __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
665  } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
666  uint32_t RESERVED0[864];
667  __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
668  uint32_t RESERVED1[15];
669  __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
670  uint32_t RESERVED2[15];
671  __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
672  uint32_t RESERVED3[29];
673  __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
674  __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
675  __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
676  uint32_t RESERVED4[43];
677  __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
678  __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
679  uint32_t RESERVED5[6];
680  __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
681  __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
682  __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
683  __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
684  __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
685  __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
686  __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
687  __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
688  __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
689  __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
690  __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
691  __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
692 } ITM_Type;
693 
694 /* ITM Trace Privilege Register Definitions */
695 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
696 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
697 
698 /* ITM Trace Control Register Definitions */
699 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
700 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
701 
702 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
703 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
704 
705 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
706 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
707 
708 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
709 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
710 
711 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
712 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
713 
714 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
715 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
716 
717 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
718 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
719 
720 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
721 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
722 
723 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
724 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
725 
726 /* ITM Integration Write Register Definitions */
727 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
728 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
729 
730 /* ITM Integration Read Register Definitions */
731 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
732 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
733 
734 /* ITM Integration Mode Control Register Definitions */
735 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
736 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
737 
738 /* ITM Lock Status Register Definitions */
739 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
740 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
741 
742 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
743 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
744 
745 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
746 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
747 
748 /*@}*/ /* end of group CMSIS_ITM */
749 
750 
751 /** \ingroup CMSIS_core_register
752  \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
753  \brief Type definitions for the Data Watchpoint and Trace (DWT)
754  @{
755  */
756 
757 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
758  */
759 typedef struct
760 {
761  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
762  __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
763  __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
764  __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
765  __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
766  __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
767  __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
768  __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
769  __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
770  __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
771  __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
772  uint32_t RESERVED0[1];
773  __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
774  __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
775  __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
776  uint32_t RESERVED1[1];
777  __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
778  __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
779  __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
780  uint32_t RESERVED2[1];
781  __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
782  __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
783  __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
784 } DWT_Type;
785 
786 /* DWT Control Register Definitions */
787 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
788 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
789 
790 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
791 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
792 
793 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
794 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
795 
796 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
797 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
798 
799 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
800 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
801 
802 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
803 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
804 
805 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
806 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
807 
808 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
809 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
810 
811 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
812 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
813 
814 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
815 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
816 
817 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
818 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
819 
820 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
821 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
822 
823 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
824 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
825 
826 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
827 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
828 
829 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
830 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
831 
832 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
833 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
834 
835 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
836 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
837 
838 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
839 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
840 
841 /* DWT CPI Count Register Definitions */
842 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
843 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
844 
845 /* DWT Exception Overhead Count Register Definitions */
846 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
847 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
848 
849 /* DWT Sleep Count Register Definitions */
850 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
851 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
852 
853 /* DWT LSU Count Register Definitions */
854 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
855 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
856 
857 /* DWT Folded-instruction Count Register Definitions */
858 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
859 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
860 
861 /* DWT Comparator Mask Register Definitions */
862 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
863 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
864 
865 /* DWT Comparator Function Register Definitions */
866 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
867 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
868 
869 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
870 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
871 
872 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
873 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
874 
875 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
876 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
877 
878 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
879 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
880 
881 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
882 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
883 
884 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
885 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
886 
887 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
888 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
889 
890 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
891 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
892 
893 /*@}*/ /* end of group CMSIS_DWT */
894 
895 
896 /** \ingroup CMSIS_core_register
897  \defgroup CMSIS_TPI Trace Port Interface (TPI)
898  \brief Type definitions for the Trace Port Interface (TPI)
899  @{
900  */
901 
902 /** \brief Structure type to access the Trace Port Interface Register (TPI).
903  */
904 typedef struct
905 {
906  __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
907  __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
908  uint32_t RESERVED0[2];
909  __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
910  uint32_t RESERVED1[55];
911  __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
912  uint32_t RESERVED2[131];
913  __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
914  __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
915  __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
916  uint32_t RESERVED3[759];
917  __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
918  __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
919  __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
920  uint32_t RESERVED4[1];
921  __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
922  __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
923  __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
924  uint32_t RESERVED5[39];
925  __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
926  __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
927  uint32_t RESERVED7[8];
928  __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
929  __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
930 } TPI_Type;
931 
932 /* TPI Asynchronous Clock Prescaler Register Definitions */
933 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
934 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
935 
936 /* TPI Selected Pin Protocol Register Definitions */
937 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
938 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
939 
940 /* TPI Formatter and Flush Status Register Definitions */
941 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
942 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
943 
944 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
945 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
946 
947 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
948 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
949 
950 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
951 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
952 
953 /* TPI Formatter and Flush Control Register Definitions */
954 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
955 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
956 
957 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
958 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
959 
960 /* TPI TRIGGER Register Definitions */
961 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
962 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
963 
964 /* TPI Integration ETM Data Register Definitions (FIFO0) */
965 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
966 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
967 
968 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
969 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
970 
971 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
972 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
973 
974 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
975 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
976 
977 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
978 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
979 
980 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
981 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
982 
983 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
984 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
985 
986 /* TPI ITATBCTR2 Register Definitions */
987 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
988 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
989 
990 /* TPI Integration ITM Data Register Definitions (FIFO1) */
991 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
992 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
993 
994 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
995 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
996 
997 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
998 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
999 
1000 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
1001 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1002 
1003 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
1004 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1005 
1006 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
1007 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1008 
1009 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
1010 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
1011 
1012 /* TPI ITATBCTR0 Register Definitions */
1013 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
1014 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
1015 
1016 /* TPI Integration Mode Control Register Definitions */
1017 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
1018 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
1019 
1020 /* TPI DEVID Register Definitions */
1021 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
1022 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1023 
1024 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
1025 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1026 
1027 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
1028 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1029 
1030 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
1031 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1032 
1033 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1034 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1035 
1036 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1037 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
1038 
1039 /* TPI DEVTYPE Register Definitions */
1040 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1041 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
1042 
1043 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1044 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1045 
1046 /*@}*/ /* end of group CMSIS_TPI */
1047 
1048 
1049 #if (__MPU_PRESENT == 1)
1050 /** \ingroup CMSIS_core_register
1051  \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1052  \brief Type definitions for the Memory Protection Unit (MPU)
1053  @{
1054  */
1055 
1056 /** \brief Structure type to access the Memory Protection Unit (MPU).
1057  */
1058 typedef struct
1059 {
1060  __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1061  __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1062  __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1063  __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1064  __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1065  __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1066  __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1067  __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1068  __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1069  __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1070  __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1071 } MPU_Type;
1072 
1073 /* MPU Type Register */
1074 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1075 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1076 
1077 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1078 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1079 
1080 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1081 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1082 
1083 /* MPU Control Register */
1084 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1085 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1086 
1087 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1088 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1089 
1090 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1091 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1092 
1093 /* MPU Region Number Register */
1094 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1095 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1096 
1097 /* MPU Region Base Address Register */
1098 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1099 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1100 
1101 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1102 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1103 
1104 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1105 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1106 
1107 /* MPU Region Attribute and Size Register */
1108 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1109 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1110 
1111 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1112 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1113 
1114 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1115 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1116 
1117 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1118 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1119 
1120 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1121 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1122 
1123 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1124 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1125 
1126 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1127 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1128 
1129 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1130 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1131 
1132 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1133 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1134 
1135 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1136 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1137 
1138 /*@} end of group CMSIS_MPU */
1139 #endif
1140 
1141 
1142 #if (__FPU_PRESENT == 1)
1143 /** \ingroup CMSIS_core_register
1144  \defgroup CMSIS_FPU Floating Point Unit (FPU)
1145  \brief Type definitions for the Floating Point Unit (FPU)
1146  @{
1147  */
1148 
1149 /** \brief Structure type to access the Floating Point Unit (FPU).
1150  */
1151 typedef struct
1152 {
1153  uint32_t RESERVED0[1];
1154  __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1155  __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1156  __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1157  __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1158  __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1159 } FPU_Type;
1160 
1161 /* Floating-Point Context Control Register */
1162 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
1163 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1164 
1165 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
1166 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1167 
1168 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
1169 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1170 
1171 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
1172 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1173 
1174 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
1175 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1176 
1177 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
1178 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1179 
1180 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
1181 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1182 
1183 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
1184 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1185 
1186 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
1187 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
1188 
1189 /* Floating-Point Context Address Register */
1190 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
1191 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1192 
1193 /* Floating-Point Default Status Control Register */
1194 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
1195 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1196 
1197 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
1198 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1199 
1200 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
1201 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1202 
1203 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
1204 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1205 
1206 /* Media and FP Feature Register 0 */
1207 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
1208 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1209 
1210 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
1211 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1212 
1213 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
1214 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1215 
1216 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
1217 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1218 
1219 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
1220 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1221 
1222 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
1223 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1224 
1225 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
1226 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1227 
1228 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
1229 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
1230 
1231 /* Media and FP Feature Register 1 */
1232 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
1233 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1234 
1235 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
1236 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1237 
1238 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
1239 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1240 
1241 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
1242 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
1243 
1244 /*@} end of group CMSIS_FPU */
1245 #endif
1246 
1247 
1248 /** \ingroup CMSIS_core_register
1249  \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1250  \brief Type definitions for the Core Debug Registers
1251  @{
1252  */
1253 
1254 /** \brief Structure type to access the Core Debug Register (CoreDebug).
1255  */
1256 typedef struct
1257 {
1258  __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1259  __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1260  __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1261  __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1262 } CoreDebug_Type;
1263 
1264 /* Debug Halting Control and Status Register */
1265 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1266 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1267 
1268 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1269 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1270 
1271 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1272 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1273 
1274 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1275 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1276 
1277 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1278 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1279 
1280 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1281 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1282 
1283 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1284 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1285 
1286 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1287 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1288 
1289 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1290 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1291 
1292 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1293 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1294 
1295 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1296 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1297 
1298 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1299 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1300 
1301 /* Debug Core Register Selector Register */
1302 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1303 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1304 
1305 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1306 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1307 
1308 /* Debug Exception and Monitor Control Register */
1309 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1310 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1311 
1312 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1313 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1314 
1315 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1316 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1317 
1318 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1319 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1320 
1321 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1322 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1323 
1324 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1325 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1326 
1327 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1328 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1329 
1330 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1331 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1332 
1333 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1334 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1335 
1336 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1337 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1338 
1339 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1340 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1341 
1342 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1343 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1344 
1345 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1346 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1347 
1348 /*@} end of group CMSIS_CoreDebug */
1349 
1350 
1351 /** \ingroup CMSIS_core_register
1352  \defgroup CMSIS_core_base Core Definitions
1353  \brief Definitions for base addresses, unions, and structures.
1354  @{
1355  */
1356 
1357 /* Memory mapping of Cortex-M4 Hardware */
1358 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1359 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1360 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1361 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1362 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1363 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1364 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1365 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1366 
1367 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1368 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1369 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1370 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1371 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1372 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1373 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1374 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1375 
1376 #if (__MPU_PRESENT == 1)
1377  #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1378  #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1379 #endif
1380 
1381 #if (__FPU_PRESENT == 1)
1382  #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1383  #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1384 #endif
1385 
1386 /*@} */
1387 
1388 
1389 
1390 /*******************************************************************************
1391  * Hardware Abstraction Layer
1392  Core Function Interface contains:
1393  - Core NVIC Functions
1394  - Core SysTick Functions
1395  - Core Debug Functions
1396  - Core Register Access Functions
1397  ******************************************************************************/
1398 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1399 */
1400 
1401 
1402 
1403 /* ########################## NVIC functions #################################### */
1404 /** \ingroup CMSIS_Core_FunctionInterface
1405  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1406  \brief Functions that manage interrupts and exceptions via the NVIC.
1407  @{
1408  */
1409 
1410 /** \brief Set Priority Grouping
1411 
1412  The function sets the priority grouping field using the required unlock sequence.
1413  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1414  Only values from 0..7 are used.
1415  In case of a conflict between priority grouping and available
1416  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1417 
1418  \param [in] PriorityGroup Priority grouping field.
1419  */
1420 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1421 {
1422  uint32_t reg_value;
1423  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1424 
1425  reg_value = SCB->AIRCR; /* read old register configuration */
1426  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1427  reg_value = (reg_value |
1428  ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1429  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1430  SCB->AIRCR = reg_value;
1431 }
1432 
1433 
1434 /** \brief Get Priority Grouping
1435 
1436  The function reads the priority grouping field from the NVIC Interrupt Controller.
1437 
1438  \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1439  */
1440 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1441 {
1442  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1443 }
1444 
1445 
1446 /** \brief Enable External Interrupt
1447 
1448  The function enables a device-specific interrupt in the NVIC interrupt controller.
1449 
1450  \param [in] IRQn External interrupt number. Value cannot be negative.
1451  */
1452 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1453 {
1454 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
1455  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
1456 }
1457 
1458 
1459 /** \brief Disable External Interrupt
1460 
1461  The function disables a device-specific interrupt in the NVIC interrupt controller.
1462 
1463  \param [in] IRQn External interrupt number. Value cannot be negative.
1464  */
1465 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1466 {
1467  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1468 }
1469 
1470 
1471 /** \brief Get Pending Interrupt
1472 
1473  The function reads the pending register in the NVIC and returns the pending bit
1474  for the specified interrupt.
1475 
1476  \param [in] IRQn Interrupt number.
1477 
1478  \return 0 Interrupt status is not pending.
1479  \return 1 Interrupt status is pending.
1480  */
1481 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1482 {
1483  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1484 }
1485 
1486 
1487 /** \brief Set Pending Interrupt
1488 
1489  The function sets the pending bit of an external interrupt.
1490 
1491  \param [in] IRQn Interrupt number. Value cannot be negative.
1492  */
1493 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1494 {
1495  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1496 }
1497 
1498 
1499 /** \brief Clear Pending Interrupt
1500 
1501  The function clears the pending bit of an external interrupt.
1502 
1503  \param [in] IRQn External interrupt number. Value cannot be negative.
1504  */
1505 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1506 {
1507  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1508 }
1509 
1510 
1511 /** \brief Get Active Interrupt
1512 
1513  The function reads the active register in NVIC and returns the active bit.
1514 
1515  \param [in] IRQn Interrupt number.
1516 
1517  \return 0 Interrupt status is not active.
1518  \return 1 Interrupt status is active.
1519  */
1520 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1521 {
1522  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1523 }
1524 
1525 
1526 /** \brief Set Interrupt Priority
1527 
1528  The function sets the priority of an interrupt.
1529 
1530  \note The priority cannot be set for every core interrupt.
1531 
1532  \param [in] IRQn Interrupt number.
1533  \param [in] priority Priority to set.
1534  */
1535 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1536 {
1537  if(IRQn < 0) {
1538  SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1539  else {
1540  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1541 }
1542 
1543 
1544 /** \brief Get Interrupt Priority
1545 
1546  The function reads the priority of an interrupt. The interrupt
1547  number can be positive to specify an external (device specific)
1548  interrupt, or negative to specify an internal (core) interrupt.
1549 
1550 
1551  \param [in] IRQn Interrupt number.
1552  \return Interrupt Priority. Value is aligned automatically to the implemented
1553  priority bits of the microcontroller.
1554  */
1555 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1556 {
1557 
1558  if(IRQn < 0) {
1559  return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1560  else {
1561  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1562 }
1563 
1564 
1565 /** \brief Encode Priority
1566 
1567  The function encodes the priority for an interrupt with the given priority group,
1568  preemptive priority value, and subpriority value.
1569  In case of a conflict between priority grouping and available
1570  priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
1571 
1572  \param [in] PriorityGroup Used priority group.
1573  \param [in] PreemptPriority Preemptive priority value (starting from 0).
1574  \param [in] SubPriority Subpriority value (starting from 0).
1575  \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1576  */
1577 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1578 {
1579  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1580  uint32_t PreemptPriorityBits;
1581  uint32_t SubPriorityBits;
1582 
1583  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1584  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1585 
1586  return (
1587  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1588  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1589  );
1590 }
1591 
1592 
1593 /** \brief Decode Priority
1594 
1595  The function decodes an interrupt priority value with a given priority group to
1596  preemptive priority value and subpriority value.
1597  In case of a conflict between priority grouping and available
1598  priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1599 
1600  \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1601  \param [in] PriorityGroup Used priority group.
1602  \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1603  \param [out] pSubPriority Subpriority value (starting from 0).
1604  */
1605 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1606 {
1607  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1608  uint32_t PreemptPriorityBits;
1609  uint32_t SubPriorityBits;
1610 
1611  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1612  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1613 
1614  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1615  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1616 }
1617 
1618 
1619 /** \brief System Reset
1620 
1621  The function initiates a system reset request to reset the MCU.
1622  */
1623 __STATIC_INLINE void NVIC_SystemReset(void)
1624 {
1625  __DSB(); /* Ensure all outstanding memory accesses included
1626  buffered write are completed before reset */
1627  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1628  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1629  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1630  __DSB(); /* Ensure completion of memory access */
1631  while(1); /* wait until reset */
1632 }
1633 
1634 /*@} end of CMSIS_Core_NVICFunctions */
1635 
1636 
1637 
1638 /* ################################## SysTick function ############################################ */
1639 /** \ingroup CMSIS_Core_FunctionInterface
1640  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1641  \brief Functions that configure the System.
1642  @{
1643  */
1644 
1645 #if (__Vendor_SysTickConfig == 0)
1646 
1647 /** \brief System Tick Configuration
1648 
1649  The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1650  Counter is in free running mode to generate periodic interrupts.
1651 
1652  \param [in] ticks Number of ticks between two interrupts.
1653 
1654  \return 0 Function succeeded.
1655  \return 1 Function failed.
1656 
1657  \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1658  function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1659  must contain a vendor-specific implementation of this function.
1660 
1661  */
1662 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1663 {
1664  if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1665 
1666  SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1667  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1668  SysTick->VAL = 0; /* Load the SysTick Counter Value */
1669  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1670  SysTick_CTRL_TICKINT_Msk |
1671  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1672  return (0); /* Function successful */
1673 }
1674 
1675 #endif
1676 
1677 /*@} end of CMSIS_Core_SysTickFunctions */
1678 
1679 
1680 
1681 /* ##################################### Debug In/Output function ########################################### */
1682 /** \ingroup CMSIS_Core_FunctionInterface
1683  \defgroup CMSIS_core_DebugFunctions ITM Functions
1684  \brief Functions that access the ITM debug interface.
1685  @{
1686  */
1687 
1688 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1689 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1690 
1691 
1692 /** \brief ITM Send Character
1693 
1694  The function transmits a character via the ITM channel 0, and
1695  \li Just returns when no debugger is connected that has booked the output.
1696  \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1697 
1698  \param [in] ch Character to transmit.
1699 
1700  \returns Character to transmit.
1701  */
1702 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1703 {
1704  if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1705  (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1706  {
1707  while (ITM->PORT[0].u32 == 0);
1708  ITM->PORT[0].u8 = (uint8_t) ch;
1709  }
1710  return (ch);
1711 }
1712 
1713 
1714 /** \brief ITM Receive Character
1715 
1716  The function inputs a character via the external variable \ref ITM_RxBuffer.
1717 
1718  \return Received character.
1719  \return -1 No character pending.
1720  */
1721 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1722  int32_t ch = -1; /* no character available */
1723 
1724  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1725  ch = ITM_RxBuffer;
1726  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1727  }
1728 
1729  return (ch);
1730 }
1731 
1732 
1733 /** \brief ITM Check Character
1734 
1735  The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1736 
1737  \return 0 No character available.
1738  \return 1 Character available.
1739  */
1740 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1741 
1742  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1743  return (0); /* no character available */
1744  } else {
1745  return (1); /* character available */
1746  }
1747 }
1748 
1749 /*@} end of CMSIS_core_DebugFunctions */
1750 
1751 #endif /* __CORE_CM4_H_DEPENDANT */
1752 
1753 #endif /* __CMSIS_GENERIC */
1754 
1755 #ifdef __cplusplus
1756 }
1757 #endif