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Data Fields
TPI_Type Struct Reference
Trace Port Interface (TPI)

Structure type to access the Trace Port Interface Register (TPI). More...

#include <core_cm3.h>

Data Fields

__IO uint32_t ACPR
__IO uint32_t CLAIMCLR
__IO uint32_t CLAIMSET
__IO uint32_t CSPSR
__I uint32_t DEVID
__I uint32_t DEVTYPE
__IO uint32_t FFCR
__I uint32_t FFSR
__I uint32_t FIFO0
__I uint32_t FIFO1
__I uint32_t FSCR
__I uint32_t ITATBCTR0
__I uint32_t ITATBCTR2
__IO uint32_t ITCTRL
uint32_t RESERVED0 [2]
uint32_t RESERVED1 [55]
uint32_t RESERVED2 [131]
uint32_t RESERVED3 [759]
uint32_t RESERVED4 [1]
uint32_t RESERVED5 [39]
uint32_t RESERVED7 [8]
__IO uint32_t SPPR
__IO uint32_t SSPSR
__I uint32_t TRIGGER

Detailed Description

Structure type to access the Trace Port Interface Register (TPI).

Definition at line 871 of file core_cm3.h.

Field Documentation

__IO uint32_t TPI_Type::ACPR

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

Definition at line 876 of file core_cm3.h.

__IO uint32_t TPI_Type::CLAIMCLR

Offset: 0xFA4 (R/W) Claim tag clear

Definition at line 893 of file core_cm3.h.

__IO uint32_t TPI_Type::CLAIMSET

Offset: 0xFA0 (R/W) Claim tag set

Definition at line 892 of file core_cm3.h.

__IO uint32_t TPI_Type::CSPSR

Offset: 0x004 (R/W) Current Parallel Port Size Register

Definition at line 874 of file core_cm3.h.

__I uint32_t TPI_Type::DEVID

Offset: 0xFC8 (R/ ) TPIU_DEVID

Definition at line 895 of file core_cm3.h.

__I uint32_t TPI_Type::DEVTYPE

Offset: 0xFCC (R/ ) TPIU_DEVTYPE

Definition at line 896 of file core_cm3.h.

__IO uint32_t TPI_Type::FFCR

Offset: 0x304 (R/W) Formatter and Flush Control Register

Definition at line 881 of file core_cm3.h.

__I uint32_t TPI_Type::FFSR

Offset: 0x300 (R/ ) Formatter and Flush Status Register

Definition at line 880 of file core_cm3.h.

__I uint32_t TPI_Type::FIFO0

Offset: 0xEEC (R/ ) Integration ETM Data

Definition at line 885 of file core_cm3.h.

__I uint32_t TPI_Type::FIFO1

Offset: 0xEFC (R/ ) Integration ITM Data

Definition at line 889 of file core_cm3.h.

__I uint32_t TPI_Type::FSCR

Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

Definition at line 882 of file core_cm3.h.

__I uint32_t TPI_Type::ITATBCTR0

Offset: 0xEF8 (R/ ) ITATBCTR0

Definition at line 888 of file core_cm3.h.

__I uint32_t TPI_Type::ITATBCTR2

Offset: 0xEF0 (R/ ) ITATBCTR2

Definition at line 886 of file core_cm3.h.

__IO uint32_t TPI_Type::ITCTRL

Offset: 0xF00 (R/W) Integration Mode Control

Definition at line 890 of file core_cm3.h.

uint32_t TPI_Type::RESERVED0

Definition at line 875 of file core_cm3.h.

uint32_t TPI_Type::RESERVED1

Definition at line 877 of file core_cm3.h.

uint32_t TPI_Type::RESERVED2

Definition at line 879 of file core_cm3.h.

uint32_t TPI_Type::RESERVED3

Definition at line 883 of file core_cm3.h.

uint32_t TPI_Type::RESERVED4

Definition at line 887 of file core_cm3.h.

uint32_t TPI_Type::RESERVED5

Definition at line 891 of file core_cm3.h.

uint32_t TPI_Type::RESERVED7

Definition at line 894 of file core_cm3.h.

__IO uint32_t TPI_Type::SPPR

Offset: 0x0F0 (R/W) Selected Pin Protocol Register

Definition at line 878 of file core_cm3.h.

__IO uint32_t TPI_Type::SSPSR

Offset: 0x000 (R/ ) Supported Parallel Port Size Register

Definition at line 873 of file core_cm3.h.

__I uint32_t TPI_Type::TRIGGER

Offset: 0xEE8 (R/ ) TRIGGER

Definition at line 884 of file core_cm3.h.

The documentation for this struct was generated from the following files: