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core_sc300.h
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1 /**************************************************************************//**
2  * @file core_sc300.h
3  * @brief CMSIS SC300 Core Peripheral Access Layer Header File
4  * @version V3.01
5  * @date 22. March 2012
6  *
7  * @note
8  * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9  *
10  * @par
11  * ARM Limited (ARM) is supplying this software for use with Cortex-M
12  * processor based microcontrollers. This file can be freely distributed
13  * within development tools that are supporting such ARM based processors.
14  *
15  * @par
16  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21  *
22  ******************************************************************************/
23 #if defined ( __ICCARM__ )
24  #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 #ifndef __CORE_SC300_H_GENERIC
32 #define __CORE_SC300_H_GENERIC
33 
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35  CMSIS violates the following MISRA-C:2004 rules:
36 
37  \li Required Rule 8.5, object/function definition in header file.<br>
38  Function definitions in header files are used to allow 'inlining'.
39 
40  \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41  Unions are used for effective representation of core registers.
42 
43  \li Advisory Rule 19.7, Function-like macro defined.<br>
44  Function-like macros are used to allow more efficient code.
45  */
46 
47 
48 /*******************************************************************************
49  * CMSIS definitions
50  ******************************************************************************/
51 /** \ingroup SC3000
52  @{
53  */
54 
55 /* CMSIS SC300 definitions */
56 #define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __SC300_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
58 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
59  __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
60 
61 #define __CORTEX_SC (300) /*!< Cortex secure core */
62 
63 
64 #if defined ( __CC_ARM )
65  #define __ASM __asm /*!< asm keyword for ARM Compiler */
66  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67  #define __STATIC_INLINE static __inline
68 
69 #elif defined ( __ICCARM__ )
70  #define __ASM __asm /*!< asm keyword for IAR Compiler */
71  #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72  #define __STATIC_INLINE static inline
73 
74 #elif defined ( __GNUC__ )
75  #define __ASM __asm /*!< asm keyword for GNU Compiler */
76  #define __INLINE inline /*!< inline keyword for GNU Compiler */
77  #define __STATIC_INLINE static inline
78 
79 #elif defined ( __TASKING__ )
80  #define __ASM __asm /*!< asm keyword for TASKING Compiler */
81  #define __INLINE inline /*!< inline keyword for TASKING Compiler */
82  #define __STATIC_INLINE static inline
83 
84 #endif
85 
86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
87 */
88 #define __FPU_USED 0
89 
90 #if defined ( __CC_ARM )
91  #if defined __TARGET_FPU_VFP
92  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93  #endif
94 
95 #elif defined ( __ICCARM__ )
96  #if defined __ARMVFP__
97  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98  #endif
99 
100 #elif defined ( __GNUC__ )
101  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103  #endif
104 
105 #elif defined ( __TASKING__ )
106  #if defined __FPU_VFP__
107  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108  #endif
109 #endif
110 
111 #include <stdint.h> /* standard types definitions */
112 #include <core_cmInstr.h> /* Core Instruction Access */
113 #include <core_cmFunc.h> /* Core Function Access */
114 
115 #endif /* __CORE_SC300_H_GENERIC */
116 
117 #ifndef __CMSIS_GENERIC
118 
119 #ifndef __CORE_SC300_H_DEPENDANT
120 #define __CORE_SC300_H_DEPENDANT
121 
122 /* check device defines and use defaults */
123 #if defined __CHECK_DEVICE_DEFINES
124  #ifndef __SC300_REV
125  #define __SC300_REV 0x0000
126  #warning "__SC300_REV not defined in device header file; using default!"
127  #endif
128 
129  #ifndef __MPU_PRESENT
130  #define __MPU_PRESENT 0
131  #warning "__MPU_PRESENT not defined in device header file; using default!"
132  #endif
133 
134  #ifndef __NVIC_PRIO_BITS
135  #define __NVIC_PRIO_BITS 4
136  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
137  #endif
138 
139  #ifndef __Vendor_SysTickConfig
140  #define __Vendor_SysTickConfig 0
141  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
142  #endif
143 #endif
144 
145 /* IO definitions (access restrictions to peripheral registers) */
146 /**
147  \defgroup CMSIS_glob_defs CMSIS Global Defines
148 
149  <strong>IO Type Qualifiers</strong> are used
150  \li to specify the access to peripheral variables.
151  \li for automatic generation of peripheral register debug information.
152 */
153 #ifdef __cplusplus
154  #define __I volatile /*!< Defines 'read only' permissions */
155 #else
156  #define __I volatile const /*!< Defines 'read only' permissions */
157 #endif
158 #define __O volatile /*!< Defines 'write only' permissions */
159 #define __IO volatile /*!< Defines 'read / write' permissions */
160 
161 /*@} end of group SC300 */
162 
163 
164 
165 /*******************************************************************************
166  * Register Abstraction
167  Core Register contain:
168  - Core Register
169  - Core NVIC Register
170  - Core SCB Register
171  - Core SysTick Register
172  - Core Debug Register
173  - Core MPU Register
174  ******************************************************************************/
175 /** \defgroup CMSIS_core_register Defines and Type Definitions
176  \brief Type definitions and defines for Cortex-M processor based devices.
177 */
178 
179 /** \ingroup CMSIS_core_register
180  \defgroup CMSIS_CORE Status and Control Registers
181  \brief Core Register type definitions.
182  @{
183  */
184 
185 /** \brief Union type to access the Application Program Status Register (APSR).
186  */
187 typedef union
188 {
189  struct
190  {
191 #if (__CORTEX_M != 0x04)
192  uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
193 #else
194  uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
195  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
196  uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
197 #endif
198  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
199  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
200  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
201  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
202  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
203  } b; /*!< Structure used for bit access */
204  uint32_t w; /*!< Type used for word access */
205 } APSR_Type;
206 
207 
208 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
209  */
210 typedef union
211 {
212  struct
213  {
214  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
215  uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
216  } b; /*!< Structure used for bit access */
217  uint32_t w; /*!< Type used for word access */
218 } IPSR_Type;
219 
220 
221 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
222  */
223 typedef union
224 {
225  struct
226  {
227  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
228 #if (__CORTEX_M != 0x04)
229  uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
230 #else
231  uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
232  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
233  uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
234 #endif
235  uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
236  uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
237  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
238  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
239  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
240  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
241  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
242  } b; /*!< Structure used for bit access */
243  uint32_t w; /*!< Type used for word access */
244 } xPSR_Type;
245 
246 
247 /** \brief Union type to access the Control Registers (CONTROL).
248  */
249 typedef union
250 {
251  struct
252  {
253  uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
254  uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
255  uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
256  uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
257  } b; /*!< Structure used for bit access */
258  uint32_t w; /*!< Type used for word access */
259 } CONTROL_Type;
260 
261 /*@} end of group CMSIS_CORE */
262 
263 
264 /** \ingroup CMSIS_core_register
265  \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
266  \brief Type definitions for the NVIC Registers
267  @{
268  */
269 
270 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
271  */
272 typedef struct
273 {
274  __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
275  uint32_t RESERVED0[24];
276  __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
277  uint32_t RSERVED1[24];
278  __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
279  uint32_t RESERVED2[24];
280  __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
281  uint32_t RESERVED3[24];
282  __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
283  uint32_t RESERVED4[56];
284  __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
285  uint32_t RESERVED5[644];
286  __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
287 } NVIC_Type;
288 
289 /* Software Triggered Interrupt Register Definitions */
290 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
291 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
292 
293 /*@} end of group CMSIS_NVIC */
294 
295 
296 /** \ingroup CMSIS_core_register
297  \defgroup CMSIS_SCB System Control Block (SCB)
298  \brief Type definitions for the System Control Block Registers
299  @{
300  */
301 
302 /** \brief Structure type to access the System Control Block (SCB).
303  */
304 typedef struct
305 {
306  __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
307  __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
308  __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
309  __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
310  __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
311  __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
312  __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
313  __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
314  __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
315  __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
316  __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
317  __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
318  __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
319  __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
320  __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
321  __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
322  __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
323  __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
324  __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
325  uint32_t RESERVED0[5];
326  __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
327 } SCB_Type;
328 
329 /* SCB CPUID Register Definitions */
330 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
331 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
332 
333 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
334 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
335 
336 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
337 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
338 
339 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
340 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
341 
342 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
343 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
344 
345 /* SCB Interrupt Control State Register Definitions */
346 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
347 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
348 
349 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
350 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
351 
352 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
353 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
354 
355 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
356 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
357 
358 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
359 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
360 
361 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
362 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
363 
364 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
365 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
366 
367 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
368 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
369 
370 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
371 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
372 
373 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
374 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
375 
376 /* SCB Vector Table Offset Register Definitions */
377 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
378 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
379 
380 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
381 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
382 
383 /* SCB Application Interrupt and Reset Control Register Definitions */
384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
386 
387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
389 
390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
392 
393 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
394 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
395 
396 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
397 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
398 
399 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
400 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
401 
402 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
403 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
404 
405 /* SCB System Control Register Definitions */
406 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
407 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
408 
409 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
410 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
411 
412 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
413 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
414 
415 /* SCB Configuration Control Register Definitions */
416 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
417 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
418 
419 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
420 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
421 
422 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
423 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
424 
425 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
426 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
427 
428 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
429 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
430 
431 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
432 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
433 
434 /* SCB System Handler Control and State Register Definitions */
435 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
436 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
437 
438 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
439 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
440 
441 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
442 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
443 
444 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
446 
447 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
448 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
449 
450 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
451 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
452 
453 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
454 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
455 
456 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
457 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
458 
459 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
460 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
461 
462 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
463 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
464 
465 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
466 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
467 
468 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
469 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
470 
471 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
472 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
473 
474 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
475 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
476 
477 /* SCB Configurable Fault Status Registers Definitions */
478 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
479 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
480 
481 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
482 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
483 
484 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
485 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
486 
487 /* SCB Hard Fault Status Registers Definitions */
488 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
489 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
490 
491 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
492 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
493 
494 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
495 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
496 
497 /* SCB Debug Fault Status Register Definitions */
498 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
499 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
500 
501 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
502 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
503 
504 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
505 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
506 
507 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
508 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
509 
510 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
511 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
512 
513 /*@} end of group CMSIS_SCB */
514 
515 
516 /** \ingroup CMSIS_core_register
517  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
518  \brief Type definitions for the System Control and ID Register not in the SCB
519  @{
520  */
521 
522 /** \brief Structure type to access the System Control and ID Register not in the SCB.
523  */
524 typedef struct
525 {
526  uint32_t RESERVED0[1];
527  __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
528  uint32_t RESERVED1[1];
529 } SCnSCB_Type;
530 
531 /* Interrupt Controller Type Register Definitions */
532 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
533 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
534 
535 /*@} end of group CMSIS_SCnotSCB */
536 
537 
538 /** \ingroup CMSIS_core_register
539  \defgroup CMSIS_SysTick System Tick Timer (SysTick)
540  \brief Type definitions for the System Timer Registers.
541  @{
542  */
543 
544 /** \brief Structure type to access the System Timer (SysTick).
545  */
546 typedef struct
547 {
548  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
549  __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
550  __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
551  __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
552 } SysTick_Type;
553 
554 /* SysTick Control / Status Register Definitions */
555 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
556 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
557 
558 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
559 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
560 
561 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
562 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
563 
564 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
565 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
566 
567 /* SysTick Reload Register Definitions */
568 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
569 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
570 
571 /* SysTick Current Register Definitions */
572 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
573 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
574 
575 /* SysTick Calibration Register Definitions */
576 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
577 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
578 
579 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
580 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
581 
582 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
583 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
584 
585 /*@} end of group CMSIS_SysTick */
586 
587 
588 /** \ingroup CMSIS_core_register
589  \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
590  \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
591  @{
592  */
593 
594 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
595  */
596 typedef struct
597 {
598  __O union
599  {
600  __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
601  __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
602  __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
603  } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
604  uint32_t RESERVED0[864];
605  __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
606  uint32_t RESERVED1[15];
607  __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
608  uint32_t RESERVED2[15];
609  __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
610  uint32_t RESERVED3[29];
611  __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
612  __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
613  __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
614  uint32_t RESERVED4[43];
615  __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
616  __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
617  uint32_t RESERVED5[6];
618  __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
619  __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
620  __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
621  __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
622  __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
623  __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
624  __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
625  __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
626  __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
627  __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
628  __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
629  __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
630 } ITM_Type;
631 
632 /* ITM Trace Privilege Register Definitions */
633 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
634 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
635 
636 /* ITM Trace Control Register Definitions */
637 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
638 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
639 
640 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
641 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
642 
643 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
644 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
645 
646 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
647 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
648 
649 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
650 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
651 
652 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
653 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
654 
655 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
656 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
657 
658 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
659 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
660 
661 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
662 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
663 
664 /* ITM Integration Write Register Definitions */
665 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
666 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
667 
668 /* ITM Integration Read Register Definitions */
669 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
670 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
671 
672 /* ITM Integration Mode Control Register Definitions */
673 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
674 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
675 
676 /* ITM Lock Status Register Definitions */
677 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
678 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
679 
680 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
681 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
682 
683 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
684 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
685 
686 /*@}*/ /* end of group CMSIS_ITM */
687 
688 
689 /** \ingroup CMSIS_core_register
690  \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
691  \brief Type definitions for the Data Watchpoint and Trace (DWT)
692  @{
693  */
694 
695 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
696  */
697 typedef struct
698 {
699  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
700  __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
701  __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
702  __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
703  __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
704  __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
705  __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
706  __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
707  __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
708  __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
709  __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
710  uint32_t RESERVED0[1];
711  __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
712  __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
713  __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
714  uint32_t RESERVED1[1];
715  __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
716  __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
717  __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
718  uint32_t RESERVED2[1];
719  __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
720  __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
721  __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
722 } DWT_Type;
723 
724 /* DWT Control Register Definitions */
725 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
726 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
727 
728 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
729 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
730 
731 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
732 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
733 
734 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
735 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
736 
737 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
738 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
739 
740 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
741 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
742 
743 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
744 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
745 
746 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
747 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
748 
749 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
750 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
751 
752 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
753 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
754 
755 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
756 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
757 
758 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
759 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
760 
761 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
762 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
763 
764 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
765 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
766 
767 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
768 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
769 
770 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
771 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
772 
773 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
774 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
775 
776 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
777 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
778 
779 /* DWT CPI Count Register Definitions */
780 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
781 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
782 
783 /* DWT Exception Overhead Count Register Definitions */
784 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
785 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
786 
787 /* DWT Sleep Count Register Definitions */
788 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
789 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
790 
791 /* DWT LSU Count Register Definitions */
792 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
793 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
794 
795 /* DWT Folded-instruction Count Register Definitions */
796 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
797 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
798 
799 /* DWT Comparator Mask Register Definitions */
800 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
801 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
802 
803 /* DWT Comparator Function Register Definitions */
804 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
805 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
806 
807 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
808 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
809 
810 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
811 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
812 
813 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
814 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
815 
816 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
817 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
818 
819 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
820 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
821 
822 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
823 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
824 
825 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
826 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
827 
828 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
829 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
830 
831 /*@}*/ /* end of group CMSIS_DWT */
832 
833 
834 /** \ingroup CMSIS_core_register
835  \defgroup CMSIS_TPI Trace Port Interface (TPI)
836  \brief Type definitions for the Trace Port Interface (TPI)
837  @{
838  */
839 
840 /** \brief Structure type to access the Trace Port Interface Register (TPI).
841  */
842 typedef struct
843 {
844  __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
845  __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
846  uint32_t RESERVED0[2];
847  __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
848  uint32_t RESERVED1[55];
849  __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
850  uint32_t RESERVED2[131];
851  __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
852  __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
853  __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
854  uint32_t RESERVED3[759];
855  __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
856  __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
857  __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
858  uint32_t RESERVED4[1];
859  __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
860  __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
861  __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
862  uint32_t RESERVED5[39];
863  __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
864  __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
865  uint32_t RESERVED7[8];
866  __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
867  __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
868 } TPI_Type;
869 
870 /* TPI Asynchronous Clock Prescaler Register Definitions */
871 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
872 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
873 
874 /* TPI Selected Pin Protocol Register Definitions */
875 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
876 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
877 
878 /* TPI Formatter and Flush Status Register Definitions */
879 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
880 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
881 
882 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
883 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
884 
885 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
886 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
887 
888 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
889 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
890 
891 /* TPI Formatter and Flush Control Register Definitions */
892 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
893 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
894 
895 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
896 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
897 
898 /* TPI TRIGGER Register Definitions */
899 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
900 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
901 
902 /* TPI Integration ETM Data Register Definitions (FIFO0) */
903 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
904 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
905 
906 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
907 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
908 
909 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
910 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
911 
912 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
913 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
914 
915 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
916 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
917 
918 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
919 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
920 
921 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
922 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
923 
924 /* TPI ITATBCTR2 Register Definitions */
925 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
926 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
927 
928 /* TPI Integration ITM Data Register Definitions (FIFO1) */
929 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
930 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
931 
932 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
933 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
934 
935 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
936 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
937 
938 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
939 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
940 
941 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
942 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
943 
944 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
945 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
946 
947 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
948 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
949 
950 /* TPI ITATBCTR0 Register Definitions */
951 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
952 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
953 
954 /* TPI Integration Mode Control Register Definitions */
955 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
956 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
957 
958 /* TPI DEVID Register Definitions */
959 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
960 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
961 
962 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
963 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
964 
965 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
966 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
967 
968 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
969 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
970 
971 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
972 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
973 
974 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
975 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
976 
977 /* TPI DEVTYPE Register Definitions */
978 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
979 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
980 
981 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
982 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
983 
984 /*@}*/ /* end of group CMSIS_TPI */
985 
986 
987 #if (__MPU_PRESENT == 1)
988 /** \ingroup CMSIS_core_register
989  \defgroup CMSIS_MPU Memory Protection Unit (MPU)
990  \brief Type definitions for the Memory Protection Unit (MPU)
991  @{
992  */
993 
994 /** \brief Structure type to access the Memory Protection Unit (MPU).
995  */
996 typedef struct
997 {
998  __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
999  __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1000  __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1001  __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1002  __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1003  __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1004  __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1005  __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1006  __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1007  __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1008  __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1009 } MPU_Type;
1010 
1011 /* MPU Type Register */
1012 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1013 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1014 
1015 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1016 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1017 
1018 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1019 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1020 
1021 /* MPU Control Register */
1022 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1023 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1024 
1025 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1026 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1027 
1028 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1029 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1030 
1031 /* MPU Region Number Register */
1032 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1033 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1034 
1035 /* MPU Region Base Address Register */
1036 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1037 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1038 
1039 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1040 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1041 
1042 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1043 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1044 
1045 /* MPU Region Attribute and Size Register */
1046 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1047 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1048 
1049 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1050 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1051 
1052 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1053 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1054 
1055 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1056 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1057 
1058 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1059 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1060 
1061 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1062 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1063 
1064 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1065 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1066 
1067 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1068 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1069 
1070 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1071 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1072 
1073 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1074 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1075 
1076 /*@} end of group CMSIS_MPU */
1077 #endif
1078 
1079 
1080 /** \ingroup CMSIS_core_register
1081  \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1082  \brief Type definitions for the Core Debug Registers
1083  @{
1084  */
1085 
1086 /** \brief Structure type to access the Core Debug Register (CoreDebug).
1087  */
1088 typedef struct
1089 {
1090  __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1091  __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1092  __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1093  __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1094 } CoreDebug_Type;
1095 
1096 /* Debug Halting Control and Status Register */
1097 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1098 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1099 
1100 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1101 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1102 
1103 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1104 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1105 
1106 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1107 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1108 
1109 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1110 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1111 
1112 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1113 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1114 
1115 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1116 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1117 
1118 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1119 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1120 
1121 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1122 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1123 
1124 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1125 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1126 
1127 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1128 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1129 
1130 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1131 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1132 
1133 /* Debug Core Register Selector Register */
1134 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1135 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1136 
1137 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1138 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1139 
1140 /* Debug Exception and Monitor Control Register */
1141 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1142 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1143 
1144 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1145 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1146 
1147 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1148 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1149 
1150 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1151 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1152 
1153 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1154 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1155 
1156 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1157 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1158 
1159 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1160 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1161 
1162 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1163 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1164 
1165 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1166 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1167 
1168 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1169 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1170 
1171 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1172 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1173 
1174 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1175 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1176 
1177 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1178 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1179 
1180 /*@} end of group CMSIS_CoreDebug */
1181 
1182 
1183 /** \ingroup CMSIS_core_register
1184  \defgroup CMSIS_core_base Core Definitions
1185  \brief Definitions for base addresses, unions, and structures.
1186  @{
1187  */
1188 
1189 /* Memory mapping of Cortex-M3 Hardware */
1190 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1191 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1192 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1193 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1194 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1195 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1196 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1197 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1198 
1199 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1200 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1201 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1202 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1203 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1204 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1205 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1206 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1207 
1208 #if (__MPU_PRESENT == 1)
1209  #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1210  #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1211 #endif
1212 
1213 /*@} */
1214 
1215 
1216 
1217 /*******************************************************************************
1218  * Hardware Abstraction Layer
1219  Core Function Interface contains:
1220  - Core NVIC Functions
1221  - Core SysTick Functions
1222  - Core Debug Functions
1223  - Core Register Access Functions
1224  ******************************************************************************/
1225 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1226 */
1227 
1228 
1229 
1230 /* ########################## NVIC functions #################################### */
1231 /** \ingroup CMSIS_Core_FunctionInterface
1232  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1233  \brief Functions that manage interrupts and exceptions via the NVIC.
1234  @{
1235  */
1236 
1237 /** \brief Set Priority Grouping
1238 
1239  The function sets the priority grouping field using the required unlock sequence.
1240  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1241  Only values from 0..7 are used.
1242  In case of a conflict between priority grouping and available
1243  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1244 
1245  \param [in] PriorityGroup Priority grouping field.
1246  */
1247 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1248 {
1249  uint32_t reg_value;
1250  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1251 
1252  reg_value = SCB->AIRCR; /* read old register configuration */
1253  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1254  reg_value = (reg_value |
1255  ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1256  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1257  SCB->AIRCR = reg_value;
1258 }
1259 
1260 
1261 /** \brief Get Priority Grouping
1262 
1263  The function reads the priority grouping field from the NVIC Interrupt Controller.
1264 
1265  \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1266  */
1267 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1268 {
1269  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1270 }
1271 
1272 
1273 /** \brief Enable External Interrupt
1274 
1275  The function enables a device-specific interrupt in the NVIC interrupt controller.
1276 
1277  \param [in] IRQn External interrupt number. Value cannot be negative.
1278  */
1279 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1280 {
1281  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1282 }
1283 
1284 
1285 /** \brief Disable External Interrupt
1286 
1287  The function disables a device-specific interrupt in the NVIC interrupt controller.
1288 
1289  \param [in] IRQn External interrupt number. Value cannot be negative.
1290  */
1291 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1292 {
1293  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1294 }
1295 
1296 
1297 /** \brief Get Pending Interrupt
1298 
1299  The function reads the pending register in the NVIC and returns the pending bit
1300  for the specified interrupt.
1301 
1302  \param [in] IRQn Interrupt number.
1303 
1304  \return 0 Interrupt status is not pending.
1305  \return 1 Interrupt status is pending.
1306  */
1307 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1308 {
1309  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1310 }
1311 
1312 
1313 /** \brief Set Pending Interrupt
1314 
1315  The function sets the pending bit of an external interrupt.
1316 
1317  \param [in] IRQn Interrupt number. Value cannot be negative.
1318  */
1319 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1320 {
1321  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1322 }
1323 
1324 
1325 /** \brief Clear Pending Interrupt
1326 
1327  The function clears the pending bit of an external interrupt.
1328 
1329  \param [in] IRQn External interrupt number. Value cannot be negative.
1330  */
1331 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1332 {
1333  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1334 }
1335 
1336 
1337 /** \brief Get Active Interrupt
1338 
1339  The function reads the active register in NVIC and returns the active bit.
1340 
1341  \param [in] IRQn Interrupt number.
1342 
1343  \return 0 Interrupt status is not active.
1344  \return 1 Interrupt status is active.
1345  */
1346 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1347 {
1348  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1349 }
1350 
1351 
1352 /** \brief Set Interrupt Priority
1353 
1354  The function sets the priority of an interrupt.
1355 
1356  \note The priority cannot be set for every core interrupt.
1357 
1358  \param [in] IRQn Interrupt number.
1359  \param [in] priority Priority to set.
1360  */
1361 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1362 {
1363  if(IRQn < 0) {
1364  SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1365  else {
1366  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1367 }
1368 
1369 
1370 /** \brief Get Interrupt Priority
1371 
1372  The function reads the priority of an interrupt. The interrupt
1373  number can be positive to specify an external (device specific)
1374  interrupt, or negative to specify an internal (core) interrupt.
1375 
1376 
1377  \param [in] IRQn Interrupt number.
1378  \return Interrupt Priority. Value is aligned automatically to the implemented
1379  priority bits of the microcontroller.
1380  */
1381 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1382 {
1383 
1384  if(IRQn < 0) {
1385  return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1386  else {
1387  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1388 }
1389 
1390 
1391 /** \brief Encode Priority
1392 
1393  The function encodes the priority for an interrupt with the given priority group,
1394  preemptive priority value, and subpriority value.
1395  In case of a conflict between priority grouping and available
1396  priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
1397 
1398  \param [in] PriorityGroup Used priority group.
1399  \param [in] PreemptPriority Preemptive priority value (starting from 0).
1400  \param [in] SubPriority Subpriority value (starting from 0).
1401  \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1402  */
1403 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1404 {
1405  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1406  uint32_t PreemptPriorityBits;
1407  uint32_t SubPriorityBits;
1408 
1409  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1410  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1411 
1412  return (
1413  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1414  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1415  );
1416 }
1417 
1418 
1419 /** \brief Decode Priority
1420 
1421  The function decodes an interrupt priority value with a given priority group to
1422  preemptive priority value and subpriority value.
1423  In case of a conflict between priority grouping and available
1424  priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1425 
1426  \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1427  \param [in] PriorityGroup Used priority group.
1428  \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1429  \param [out] pSubPriority Subpriority value (starting from 0).
1430  */
1431 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1432 {
1433  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1434  uint32_t PreemptPriorityBits;
1435  uint32_t SubPriorityBits;
1436 
1437  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1438  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1439 
1440  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1441  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1442 }
1443 
1444 
1445 /** \brief System Reset
1446 
1447  The function initiates a system reset request to reset the MCU.
1448  */
1449 __STATIC_INLINE void NVIC_SystemReset(void)
1450 {
1451  __DSB(); /* Ensure all outstanding memory accesses included
1452  buffered write are completed before reset */
1453  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1454  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1455  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1456  __DSB(); /* Ensure completion of memory access */
1457  while(1); /* wait until reset */
1458 }
1459 
1460 /*@} end of CMSIS_Core_NVICFunctions */
1461 
1462 
1463 
1464 /* ################################## SysTick function ############################################ */
1465 /** \ingroup CMSIS_Core_FunctionInterface
1466  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1467  \brief Functions that configure the System.
1468  @{
1469  */
1470 
1471 #if (__Vendor_SysTickConfig == 0)
1472 
1473 /** \brief System Tick Configuration
1474 
1475  The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1476  Counter is in free running mode to generate periodic interrupts.
1477 
1478  \param [in] ticks Number of ticks between two interrupts.
1479 
1480  \return 0 Function succeeded.
1481  \return 1 Function failed.
1482 
1483  \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1484  function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1485  must contain a vendor-specific implementation of this function.
1486 
1487  */
1488 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1489 {
1490  if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1491 
1492  SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1493  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1494  SysTick->VAL = 0; /* Load the SysTick Counter Value */
1495  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1496  SysTick_CTRL_TICKINT_Msk |
1497  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1498  return (0); /* Function successful */
1499 }
1500 
1501 #endif
1502 
1503 /*@} end of CMSIS_Core_SysTickFunctions */
1504 
1505 
1506 
1507 /* ##################################### Debug In/Output function ########################################### */
1508 /** \ingroup CMSIS_Core_FunctionInterface
1509  \defgroup CMSIS_core_DebugFunctions ITM Functions
1510  \brief Functions that access the ITM debug interface.
1511  @{
1512  */
1513 
1514 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1515 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1516 
1517 
1518 /** \brief ITM Send Character
1519 
1520  The function transmits a character via the ITM channel 0, and
1521  \li Just returns when no debugger is connected that has booked the output.
1522  \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1523 
1524  \param [in] ch Character to transmit.
1525 
1526  \returns Character to transmit.
1527  */
1528 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1529 {
1530  if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1531  (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1532  {
1533  while (ITM->PORT[0].u32 == 0);
1534  ITM->PORT[0].u8 = (uint8_t) ch;
1535  }
1536  return (ch);
1537 }
1538 
1539 
1540 /** \brief ITM Receive Character
1541 
1542  The function inputs a character via the external variable \ref ITM_RxBuffer.
1543 
1544  \return Received character.
1545  \return -1 No character pending.
1546  */
1547 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1548  int32_t ch = -1; /* no character available */
1549 
1550  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1551  ch = ITM_RxBuffer;
1552  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1553  }
1554 
1555  return (ch);
1556 }
1557 
1558 
1559 /** \brief ITM Check Character
1560 
1561  The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1562 
1563  \return 0 No character available.
1564  \return 1 Character available.
1565  */
1566 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1567 
1568  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1569  return (0); /* no character available */
1570  } else {
1571  return (1); /* character available */
1572  }
1573 }
1574 
1575 /*@} end of CMSIS_core_DebugFunctions */
1576 
1577 #endif /* __CORE_SC300_H_DEPENDANT */
1578 
1579 #endif /* __CMSIS_GENERIC */
1580 
1581 #ifdef __cplusplus
1582 }
1583 #endif