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core_cm0plus.h
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1 /**************************************************************************//**
2  * @file core_cm0plus.h
3  * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4  * @version V3.01
5  * @date 22. March 2012
6  *
7  * @note
8  * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9  *
10  * @par
11  * ARM Limited (ARM) is supplying this software for use with Cortex-M
12  * processor based microcontrollers. This file can be freely distributed
13  * within development tools that are supporting such ARM based processors.
14  *
15  * @par
16  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21  *
22  ******************************************************************************/
23 #if defined ( __ICCARM__ )
24  #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 #ifndef __CORE_CM0PLUS_H_GENERIC
32 #define __CORE_CM0PLUS_H_GENERIC
33 
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35  CMSIS violates the following MISRA-C:2004 rules:
36 
37  \li Required Rule 8.5, object/function definition in header file.<br>
38  Function definitions in header files are used to allow 'inlining'.
39 
40  \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41  Unions are used for effective representation of core registers.
42 
43  \li Advisory Rule 19.7, Function-like macro defined.<br>
44  Function-like macros are used to allow more efficient code.
45  */
46 
47 
48 /*******************************************************************************
49  * CMSIS definitions
50  ******************************************************************************/
51 /** \ingroup Cortex-M0+
52  @{
53  */
54 
55 /* CMSIS CM0P definitions */
56 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
58 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
59  __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
60 
61 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
62 
63 
64 #if defined ( __CC_ARM )
65  #define __ASM __asm /*!< asm keyword for ARM Compiler */
66  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67  #define __STATIC_INLINE static __inline
68 
69 #elif defined ( __ICCARM__ )
70  #define __ASM __asm /*!< asm keyword for IAR Compiler */
71  #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72  #define __STATIC_INLINE static inline
73 
74 #elif defined ( __GNUC__ )
75  #define __ASM __asm /*!< asm keyword for GNU Compiler */
76  #define __INLINE inline /*!< inline keyword for GNU Compiler */
77  #define __STATIC_INLINE static inline
78 
79 #elif defined ( __TASKING__ )
80  #define __ASM __asm /*!< asm keyword for TASKING Compiler */
81  #define __INLINE inline /*!< inline keyword for TASKING Compiler */
82  #define __STATIC_INLINE static inline
83 
84 #endif
85 
86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
87 */
88 #define __FPU_USED 0
89 
90 #if defined ( __CC_ARM )
91  #if defined __TARGET_FPU_VFP
92  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93  #endif
94 
95 #elif defined ( __ICCARM__ )
96  #if defined __ARMVFP__
97  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98  #endif
99 
100 #elif defined ( __GNUC__ )
101  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103  #endif
104 
105 #elif defined ( __TASKING__ )
106  #if defined __FPU_VFP__
107  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108  #endif
109 #endif
110 
111 #include <stdint.h> /* standard types definitions */
112 #include <core_cmInstr.h> /* Core Instruction Access */
113 #include <core_cmFunc.h> /* Core Function Access */
114 
115 #endif /* __CORE_CM0PLUS_H_GENERIC */
116 
117 #ifndef __CMSIS_GENERIC
118 
119 #ifndef __CORE_CM0PLUS_H_DEPENDANT
120 #define __CORE_CM0PLUS_H_DEPENDANT
121 
122 /* check device defines and use defaults */
123 #if defined __CHECK_DEVICE_DEFINES
124  #ifndef __CM0PLUS_REV
125  #define __CM0PLUS_REV 0x0000
126  #warning "__CM0PLUS_REV not defined in device header file; using default!"
127  #endif
128 
129  #ifndef __MPU_PRESENT
130  #define __MPU_PRESENT 0
131  #warning "__MPU_PRESENT not defined in device header file; using default!"
132  #endif
133 
134  #ifndef __VTOR_PRESENT
135  #define __VTOR_PRESENT 0
136  #warning "__VTOR_PRESENT not defined in device header file; using default!"
137  #endif
138 
139  #ifndef __NVIC_PRIO_BITS
140  #define __NVIC_PRIO_BITS 2
141  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
142  #endif
143 
144  #ifndef __Vendor_SysTickConfig
145  #define __Vendor_SysTickConfig 0
146  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
147  #endif
148 #endif
149 
150 /* IO definitions (access restrictions to peripheral registers) */
151 /**
152  \defgroup CMSIS_glob_defs CMSIS Global Defines
153 
154  <strong>IO Type Qualifiers</strong> are used
155  \li to specify the access to peripheral variables.
156  \li for automatic generation of peripheral register debug information.
157 */
158 #ifdef __cplusplus
159  #define __I volatile /*!< Defines 'read only' permissions */
160 #else
161  #define __I volatile const /*!< Defines 'read only' permissions */
162 #endif
163 #define __O volatile /*!< Defines 'write only' permissions */
164 #define __IO volatile /*!< Defines 'read / write' permissions */
165 
166 /*@} end of group Cortex-M0+ */
167 
168 
169 
170 /*******************************************************************************
171  * Register Abstraction
172  Core Register contain:
173  - Core Register
174  - Core NVIC Register
175  - Core SCB Register
176  - Core SysTick Register
177  - Core MPU Register
178  ******************************************************************************/
179 /** \defgroup CMSIS_core_register Defines and Type Definitions
180  \brief Type definitions and defines for Cortex-M processor based devices.
181 */
182 
183 /** \ingroup CMSIS_core_register
184  \defgroup CMSIS_CORE Status and Control Registers
185  \brief Core Register type definitions.
186  @{
187  */
188 
189 /** \brief Union type to access the Application Program Status Register (APSR).
190  */
191 typedef union
192 {
193  struct
194  {
195 #if (__CORTEX_M != 0x04)
196  uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
197 #else
198  uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
199  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
200  uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
201 #endif
202  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
203  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
204  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
205  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
206  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
207  } b; /*!< Structure used for bit access */
208  uint32_t w; /*!< Type used for word access */
209 } APSR_Type;
210 
211 
212 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
213  */
214 typedef union
215 {
216  struct
217  {
218  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
219  uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
220  } b; /*!< Structure used for bit access */
221  uint32_t w; /*!< Type used for word access */
222 } IPSR_Type;
223 
224 
225 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
226  */
227 typedef union
228 {
229  struct
230  {
231  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
232 #if (__CORTEX_M != 0x04)
233  uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
234 #else
235  uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
236  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
237  uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
238 #endif
239  uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
240  uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
241  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
242  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
243  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
244  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
245  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
246  } b; /*!< Structure used for bit access */
247  uint32_t w; /*!< Type used for word access */
248 } xPSR_Type;
249 
250 
251 /** \brief Union type to access the Control Registers (CONTROL).
252  */
253 typedef union
254 {
255  struct
256  {
257  uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
258  uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
259  uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
260  uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
261  } b; /*!< Structure used for bit access */
262  uint32_t w; /*!< Type used for word access */
263 } CONTROL_Type;
264 
265 /*@} end of group CMSIS_CORE */
266 
267 
268 /** \ingroup CMSIS_core_register
269  \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
270  \brief Type definitions for the NVIC Registers
271  @{
272  */
273 
274 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
275  */
276 typedef struct
277 {
278  __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
279  uint32_t RESERVED0[31];
280  __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
281  uint32_t RSERVED1[31];
282  __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
283  uint32_t RESERVED2[31];
284  __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
285  uint32_t RESERVED3[31];
286  uint32_t RESERVED4[64];
287  __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
288 } NVIC_Type;
289 
290 /*@} end of group CMSIS_NVIC */
291 
292 
293 /** \ingroup CMSIS_core_register
294  \defgroup CMSIS_SCB System Control Block (SCB)
295  \brief Type definitions for the System Control Block Registers
296  @{
297  */
298 
299 /** \brief Structure type to access the System Control Block (SCB).
300  */
301 typedef struct
302 {
303  __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
304  __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
305 #if (__VTOR_PRESENT == 1)
306  __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
307 #else
308  uint32_t RESERVED0;
309 #endif
310  __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
311  __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
312  __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
313  uint32_t RESERVED1;
314  __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
315  __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
316 } SCB_Type;
317 
318 /* SCB CPUID Register Definitions */
319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
321 
322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
324 
325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
327 
328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
330 
331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
333 
334 /* SCB Interrupt Control State Register Definitions */
335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
337 
338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
340 
341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
343 
344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
346 
347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
349 
350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
352 
353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
355 
356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
358 
359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
361 
362 #if (__VTOR_PRESENT == 1)
363 /* SCB Interrupt Control State Register Definitions */
364 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
365 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
366 #endif
367 
368 /* SCB Application Interrupt and Reset Control Register Definitions */
369 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
370 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
371 
372 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
373 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
374 
375 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
376 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
377 
378 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
379 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
380 
381 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
382 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
383 
384 /* SCB System Control Register Definitions */
385 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
386 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
387 
388 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
389 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
390 
391 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
392 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
393 
394 /* SCB Configuration Control Register Definitions */
395 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
396 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
397 
398 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
399 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
400 
401 /* SCB System Handler Control and State Register Definitions */
402 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
403 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
404 
405 /*@} end of group CMSIS_SCB */
406 
407 
408 /** \ingroup CMSIS_core_register
409  \defgroup CMSIS_SysTick System Tick Timer (SysTick)
410  \brief Type definitions for the System Timer Registers.
411  @{
412  */
413 
414 /** \brief Structure type to access the System Timer (SysTick).
415  */
416 typedef struct
417 {
418  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
419  __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
420  __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
421  __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
422 } SysTick_Type;
423 
424 /* SysTick Control / Status Register Definitions */
425 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
426 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
427 
428 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
429 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
430 
431 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
432 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
433 
434 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
435 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
436 
437 /* SysTick Reload Register Definitions */
438 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
439 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
440 
441 /* SysTick Current Register Definitions */
442 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
443 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
444 
445 /* SysTick Calibration Register Definitions */
446 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
447 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
448 
449 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
450 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
451 
452 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
453 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
454 
455 /*@} end of group CMSIS_SysTick */
456 
457 #if (__MPU_PRESENT == 1)
458 /** \ingroup CMSIS_core_register
459  \defgroup CMSIS_MPU Memory Protection Unit (MPU)
460  \brief Type definitions for the Memory Protection Unit (MPU)
461  @{
462  */
463 
464 /** \brief Structure type to access the Memory Protection Unit (MPU).
465  */
466 typedef struct
467 {
468  __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
469  __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
470  __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
471  __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
472  __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
473 } MPU_Type;
474 
475 /* MPU Type Register */
476 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
477 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
478 
479 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
480 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
481 
482 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
483 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
484 
485 /* MPU Control Register */
486 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
487 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
488 
489 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
490 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
491 
492 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
493 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
494 
495 /* MPU Region Number Register */
496 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
497 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
498 
499 /* MPU Region Base Address Register */
500 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
501 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
502 
503 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
504 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
505 
506 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
507 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
508 
509 /* MPU Region Attribute and Size Register */
510 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
511 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
512 
513 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
514 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
515 
516 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
517 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
518 
519 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
520 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
521 
522 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
523 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
524 
525 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
526 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
527 
528 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
529 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
530 
531 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
532 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
533 
534 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
535 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
536 
537 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
538 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
539 
540 /*@} end of group CMSIS_MPU */
541 #endif
542 
543 
544 /** \ingroup CMSIS_core_register
545  \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
546  \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
547  are only accessible over DAP and not via processor. Therefore
548  they are not covered by the Cortex-M0 header file.
549  @{
550  */
551 /*@} end of group CMSIS_CoreDebug */
552 
553 
554 /** \ingroup CMSIS_core_register
555  \defgroup CMSIS_core_base Core Definitions
556  \brief Definitions for base addresses, unions, and structures.
557  @{
558  */
559 
560 /* Memory mapping of Cortex-M0+ Hardware */
561 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
562 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
563 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
564 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
565 
566 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
567 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
568 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
569 
570 #if (__MPU_PRESENT == 1)
571  #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
572  #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
573 #endif
574 
575 /*@} */
576 
577 
578 
579 /*******************************************************************************
580  * Hardware Abstraction Layer
581  Core Function Interface contains:
582  - Core NVIC Functions
583  - Core SysTick Functions
584  - Core Register Access Functions
585  ******************************************************************************/
586 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
587 */
588 
589 
590 
591 /* ########################## NVIC functions #################################### */
592 /** \ingroup CMSIS_Core_FunctionInterface
593  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
594  \brief Functions that manage interrupts and exceptions via the NVIC.
595  @{
596  */
597 
598 /* Interrupt Priorities are WORD accessible only under ARMv6M */
599 /* The following MACROS handle generation of the register offset and byte masks */
600 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
601 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
602 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
603 
604 
605 /** \brief Enable External Interrupt
606 
607  The function enables a device-specific interrupt in the NVIC interrupt controller.
608 
609  \param [in] IRQn External interrupt number. Value cannot be negative.
610  */
611 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
612 {
613  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
614 }
615 
616 
617 /** \brief Disable External Interrupt
618 
619  The function disables a device-specific interrupt in the NVIC interrupt controller.
620 
621  \param [in] IRQn External interrupt number. Value cannot be negative.
622  */
623 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
624 {
625  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
626 }
627 
628 
629 /** \brief Get Pending Interrupt
630 
631  The function reads the pending register in the NVIC and returns the pending bit
632  for the specified interrupt.
633 
634  \param [in] IRQn Interrupt number.
635 
636  \return 0 Interrupt status is not pending.
637  \return 1 Interrupt status is pending.
638  */
639 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
640 {
641  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
642 }
643 
644 
645 /** \brief Set Pending Interrupt
646 
647  The function sets the pending bit of an external interrupt.
648 
649  \param [in] IRQn Interrupt number. Value cannot be negative.
650  */
651 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
652 {
653  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
654 }
655 
656 
657 /** \brief Clear Pending Interrupt
658 
659  The function clears the pending bit of an external interrupt.
660 
661  \param [in] IRQn External interrupt number. Value cannot be negative.
662  */
663 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
664 {
665  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
666 }
667 
668 
669 /** \brief Set Interrupt Priority
670 
671  The function sets the priority of an interrupt.
672 
673  \note The priority cannot be set for every core interrupt.
674 
675  \param [in] IRQn Interrupt number.
676  \param [in] priority Priority to set.
677  */
678 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
679 {
680  if(IRQn < 0) {
681  SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
682  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
683  else {
684  NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
685  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
686 }
687 
688 
689 /** \brief Get Interrupt Priority
690 
691  The function reads the priority of an interrupt. The interrupt
692  number can be positive to specify an external (device specific)
693  interrupt, or negative to specify an internal (core) interrupt.
694 
695 
696  \param [in] IRQn Interrupt number.
697  \return Interrupt Priority. Value is aligned automatically to the implemented
698  priority bits of the microcontroller.
699  */
700 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
701 {
702 
703  if(IRQn < 0) {
704  return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */
705  else {
706  return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
707 }
708 
709 
710 /** \brief System Reset
711 
712  The function initiates a system reset request to reset the MCU.
713  */
714 __STATIC_INLINE void NVIC_SystemReset(void)
715 {
716  __DSB(); /* Ensure all outstanding memory accesses included
717  buffered write are completed before reset */
718  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
719  SCB_AIRCR_SYSRESETREQ_Msk);
720  __DSB(); /* Ensure completion of memory access */
721  while(1); /* wait until reset */
722 }
723 
724 /*@} end of CMSIS_Core_NVICFunctions */
725 
726 
727 
728 /* ################################## SysTick function ############################################ */
729 /** \ingroup CMSIS_Core_FunctionInterface
730  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
731  \brief Functions that configure the System.
732  @{
733  */
734 
735 #if (__Vendor_SysTickConfig == 0)
736 
737 /** \brief System Tick Configuration
738 
739  The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
740  Counter is in free running mode to generate periodic interrupts.
741 
742  \param [in] ticks Number of ticks between two interrupts.
743 
744  \return 0 Function succeeded.
745  \return 1 Function failed.
746 
747  \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
748  function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
749  must contain a vendor-specific implementation of this function.
750 
751  */
752 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
753 {
754  if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
755 
756  SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
757  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
758  SysTick->VAL = 0; /* Load the SysTick Counter Value */
759  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
760  SysTick_CTRL_TICKINT_Msk |
761  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
762  return (0); /* Function successful */
763 }
764 
765 #endif
766 
767 /*@} end of CMSIS_Core_SysTickFunctions */
768 
769 
770 
771 
772 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
773 
774 #endif /* __CMSIS_GENERIC */
775 
776 #ifdef __cplusplus
777 }
778 #endif