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LPC17xx.h
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1 /**************************************************************************//**
2  * @file LPC17xx/Include/LPC17xx.h
3  * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
4  * NXP LPC17xx Device Series
5  * @version: V1.09
6  * @date: 25. July. 2011
7  *
8  * @note
9  * Copyright (C) 2009 ARM Limited. All rights reserved.
10  *
11  * @par
12  * ARM Limited (ARM) is supplying this software for use with Cortex-M
13  * processor based microcontrollers. This file can be freely distributed
14  * within development tools that are supporting such ARM based processors.
15  *
16  * @par
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  ******************************************************************************/
24 
25 
26 #ifndef __LPC17xx_H__
27 #define __LPC17xx_H__
28 
29 /* default MCU_MODEL ----------------------------------------------------------- */
30 #ifndef i_MCU_MODEL
31  #define i_MCU_MODEL 1761
32  #ifndef i_ARCH
33  #define i_ARCH CM3
34  #endif
35 #endif
36 /*
37  * ==========================================================================
38  * ---------- Interrupt Number Definition -----------------------------------
39  * ==========================================================================
40  */
41 
42 /** @addtogroup LPC17xx_System
43  * @{
44  */
45 
46 /** @brief IRQ interrupt source definition */
47 typedef enum IRQn
48 {
49 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
50  NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
51  MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
52  BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
53  UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
54  SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
55  DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
56  PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
57  SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
58 
59 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
60  WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
61  TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
62  TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
63  TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
64  TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
65  UART0_IRQn = 5, /*!< UART0 Interrupt */
66  UART1_IRQn = 6, /*!< UART1 Interrupt */
67  UART2_IRQn = 7, /*!< UART2 Interrupt */
68  UART3_IRQn = 8, /*!< UART3 Interrupt */
69  PWM1_IRQn = 9, /*!< PWM1 Interrupt */
70  I2C0_IRQn = 10, /*!< I2C0 Interrupt */
71  I2C1_IRQn = 11, /*!< I2C1 Interrupt */
72  I2C2_IRQn = 12, /*!< I2C2 Interrupt */
73  SPI_IRQn = 13, /*!< SPI Interrupt */
74  SSP0_IRQn = 14, /*!< SSP0 Interrupt */
75  SSP1_IRQn = 15, /*!< SSP1 Interrupt */
76  PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
77  RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
78  EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
79  EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
80  EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
81  EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
82  ADC_IRQn = 22, /*!< A/D Converter Interrupt */
83  BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
84  USB_IRQn = 24, /*!< USB Interrupt */
85  CAN_IRQn = 25, /*!< CAN Interrupt */
86  DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
87  I2S_IRQn = 27, /*!< I2S Interrupt */
88  ENET_IRQn = 28, /*!< Ethernet Interrupt */
89  RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
90  MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
91  QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
92  PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
93  USBActivity_IRQn = 33, /*!< USB Activity Interrupt */
94  CANActivity_IRQn = 34 /*!< CAN Activity Interrupt */
95 } IRQn_Type;
96 
97 
98 /*
99  * ==========================================================================
100  * ----------- Processor and Core Peripheral Section ------------------------
101  * ==========================================================================
102  */
103 
104 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
105 #define __MPU_PRESENT 1 /*!< MPU present or not */
106 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
107 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
108 
109 
110 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
111 #include "system_LPC17xx.h" /* System Header */
112 
113 
114 /******************************************************************************/
115 /* Device Specific Peripheral registers structures */
116 /******************************************************************************/
117 
118 #if defined ( __CC_ARM )
119 #pragma anon_unions
120 #endif
121 
122 /*------------- System Control (SC) ------------------------------------------*/
123 /** @brief System Control (SC) register structure definition */
124 typedef struct
125 {
126  __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
127  uint32_t RESERVED0[31];
128  __IO uint32_t PLL0CON; /* Clocking and Power Control */
129  __IO uint32_t PLL0CFG;
130  __I uint32_t PLL0STAT;
131  __O uint32_t PLL0FEED;
132  uint32_t RESERVED1[4];
133  __IO uint32_t PLL1CON;
134  __IO uint32_t PLL1CFG;
135  __I uint32_t PLL1STAT;
136  __O uint32_t PLL1FEED;
137  uint32_t RESERVED2[4];
138  __IO uint32_t PCON;
139  __IO uint32_t PCONP;
140  uint32_t RESERVED3[15];
141  __IO uint32_t CCLKCFG;
142  __IO uint32_t USBCLKCFG;
143  __IO uint32_t CLKSRCSEL;
144  __IO uint32_t CANSLEEPCLR;
145  __IO uint32_t CANWAKEFLAGS;
146  uint32_t RESERVED4[10];
147  __IO uint32_t EXTINT; /* External Interrupts */
148  uint32_t RESERVED5;
149  __IO uint32_t EXTMODE;
150  __IO uint32_t EXTPOLAR;
151  uint32_t RESERVED6[12];
152  __IO uint32_t RSID; /* Reset */
153  uint32_t RESERVED7[7];
154  __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
155  __IO uint32_t IRCTRIM; /* Clock Dividers */
156  __IO uint32_t PCLKSEL0;
157  __IO uint32_t PCLKSEL1;
158  uint32_t RESERVED8[4];
159  __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
160  __IO uint32_t DMAREQSEL;
161  __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
162  } LPC_SC_TypeDef;
163 
164 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
165 /** @brief Pin Connect Block (PINCON) register structure definition */
166 typedef struct
167 {
168  __IO uint32_t PINSEL0;
169  __IO uint32_t PINSEL1;
170  __IO uint32_t PINSEL2;
171  __IO uint32_t PINSEL3;
172  __IO uint32_t PINSEL4;
173  __IO uint32_t PINSEL5;
174  __IO uint32_t PINSEL6;
175  __IO uint32_t PINSEL7;
176  __IO uint32_t PINSEL8;
177  __IO uint32_t PINSEL9;
178  __IO uint32_t PINSEL10;
179  uint32_t RESERVED0[5];
180  __IO uint32_t PINMODE0;
181  __IO uint32_t PINMODE1;
182  __IO uint32_t PINMODE2;
183  __IO uint32_t PINMODE3;
184  __IO uint32_t PINMODE4;
185  __IO uint32_t PINMODE5;
186  __IO uint32_t PINMODE6;
187  __IO uint32_t PINMODE7;
188  __IO uint32_t PINMODE8;
189  __IO uint32_t PINMODE9;
190  __IO uint32_t PINMODE_OD0;
191  __IO uint32_t PINMODE_OD1;
192  __IO uint32_t PINMODE_OD2;
193  __IO uint32_t PINMODE_OD3;
194  __IO uint32_t PINMODE_OD4;
195  __IO uint32_t I2CPADCFG;
196 } LPC_PINCON_TypeDef;
197 
198 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
199 /** @brief General Purpose Input/Output (GPIO) register structure definition */
200 typedef struct
201 {
202  union {
203  __IO uint32_t FIODIR;
204  struct {
205  __IO uint16_t FIODIRL;
206  __IO uint16_t FIODIRH;
207  };
208  struct {
209  __IO uint8_t FIODIR0;
210  __IO uint8_t FIODIR1;
211  __IO uint8_t FIODIR2;
212  __IO uint8_t FIODIR3;
213  };
214  };
215  uint32_t RESERVED0[3];
216  union {
217  __IO uint32_t FIOMASK;
218  struct {
219  __IO uint16_t FIOMASKL;
220  __IO uint16_t FIOMASKH;
221  };
222  struct {
223  __IO uint8_t FIOMASK0;
224  __IO uint8_t FIOMASK1;
225  __IO uint8_t FIOMASK2;
226  __IO uint8_t FIOMASK3;
227  };
228  };
229  union {
230  __IO uint32_t FIOPIN;
231  struct {
232  __IO uint16_t FIOPINL;
233  __IO uint16_t FIOPINH;
234  };
235  struct {
236  __IO uint8_t FIOPIN0;
237  __IO uint8_t FIOPIN1;
238  __IO uint8_t FIOPIN2;
239  __IO uint8_t FIOPIN3;
240  };
241  };
242  union {
243  __IO uint32_t FIOSET;
244  struct {
245  __IO uint16_t FIOSETL;
246  __IO uint16_t FIOSETH;
247  };
248  struct {
249  __IO uint8_t FIOSET0;
250  __IO uint8_t FIOSET1;
251  __IO uint8_t FIOSET2;
252  __IO uint8_t FIOSET3;
253  };
254  };
255  union {
256  __O uint32_t FIOCLR;
257  struct {
258  __O uint16_t FIOCLRL;
259  __O uint16_t FIOCLRH;
260  };
261  struct {
262  __O uint8_t FIOCLR0;
263  __O uint8_t FIOCLR1;
264  __O uint8_t FIOCLR2;
265  __O uint8_t FIOCLR3;
266  };
267  };
268 } LPC_GPIO_TypeDef;
269 
270 /** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
271 typedef struct
272 {
273  __I uint32_t IntStatus;
274  __I uint32_t IO0IntStatR;
275  __I uint32_t IO0IntStatF;
276  __O uint32_t IO0IntClr;
277  __IO uint32_t IO0IntEnR;
278  __IO uint32_t IO0IntEnF;
279  uint32_t RESERVED0[3];
280  __I uint32_t IO2IntStatR;
281  __I uint32_t IO2IntStatF;
282  __O uint32_t IO2IntClr;
283  __IO uint32_t IO2IntEnR;
284  __IO uint32_t IO2IntEnF;
285 } LPC_GPIOINT_TypeDef;
286 
287 /*------------- Timer (TIM) --------------------------------------------------*/
288 // Timer Interrupt Register Bit Definitions
289 #define TIR_MR0I_Msk (1 << 0) // Interrupt flag for match channel 0
290 #define TIR_MR1I_Msk (1 << 1) // Interrupt flag for match channel 1
291 #define TIR_MR2I_Msk (1 << 2) // Interrupt flag for match channel 2
292 #define TIR_MR3I_Msk (1 << 3) // Interrupt flag for match channel 3
293 #define TIR_CR0I_Msk (1 << 4) // Interrupt flag for capture channel 0 event
294 #define TIR_CR1I_Msk (1 << 5) // Interrupt flag for capture channel 1 event
295 #define TIR_CR2I_Msk (1 << 6) // Interrupt flag for capture channel 2 event
296 #define TIR_CR3I_Msk (1 << 7) // Interrupt flag for capture channel 3 event
297 
298 // PWM Interrupt Register Bit Definitions
299 #define PWMIR_MR0I_Msk (1 << 0) // Interrupt flag for match channel 0
300 #define PWMIR_MR1I_Msk (1 << 1) // Interrupt flag for match channel 1
301 #define PWMIR_MR2I_Msk (1 << 2) // Interrupt flag for match channel 2
302 #define PWMIR_MR3I_Msk (1 << 3) // Interrupt flag for match channel 3
303 #define PWMIR_MR4I_Msk (1 << 8) // Interrupt flag for match channel 4
304 #define PWMIR_MR5I_Msk (1 << 9) // Interrupt flag for match channel 5
305 #define PWMIR_MR6I_Msk (1 << 10) // Interrupt flag for match channel 6
306 #define PWMIR_Msk (0x070F)
307 
308 // Timer Control Register Bit Definitions
309 #define TCR_ENABLE_Msk (1 << 0)
310 #define TCR_RESET_Msk (1 << 1)
311 
312 // Timer Match Control Register Bit Definitions
313 #define TMCR_MR0_I_Msk (1 << 0) // Enable Interrupt when MR0 matches TC
314 #define TMCR_MR0_R_Msk (1 << 1) // Enable Reset of TC upon MR0 match
315 #define TMCR_MR0_S_Msk (1 << 2) // Enable Stop of TC upon MR0 match
316 #define TMCR_MR1_I_Msk (1 << 3) // Enable Interrupt when MR1 matches TC
317 #define TMCR_MR1_R_Msk (1 << 4) // Enable Reset of TC upon MR1 match
318 #define TMCR_MR1_S_Msk (1 << 5) // Enable Stop of TC upon MR1 match
319 #define TMCR_MR2_I_Msk (1 << 6) // Enable Interrupt when MR2 matches TC
320 #define TMCR_MR2_R_Msk (1 << 7) // Enable Reset of TC upon MR2 match
321 #define TMCR_MR2_S_Msk (1 << 8) // Enable Stop of TC upon MR2 match
322 #define TMCR_MR3_I_Msk (1 << 9) // Enable Interrupt when MR3 matches TC
323 #define TMCR_MR3_R_Msk (1 << 10) // Enable Reset of TC upon MR3 match
324 #define TMCR_MR3_S_Msk (1 << 11) // Enable Stop of TC upon MR3 match
325 
326 // Timer Capture Control Register Bit Definitions
327 #define TCCR_CR0_R_Msk (1 << 0) // Enable Rising edge on CAPn.0 will load TC to CR0
328 #define TCCR_CR0_F_Msk (1 << 1) // Enable Falling edge on CAPn.0 will load TC to CR0
329 #define TCCR_CR0_I_Msk (1 << 2) // Enable Interrupt on load of CR0
330 #define TCCR_CR1_R_Msk (1 << 3) // Enable Rising edge on CAPn.1 will load TC to CR1
331 #define TCCR_CR1_F_Msk (1 << 4) // Enable Falling edge on CAPn.1 will load TC to CR1
332 #define TCCR_CR1_I_Msk (1 << 5) // Enable Interrupt on load of CR1
333 #define TCCR_CR2_R_Msk (1 << 6) // Enable Rising edge on CAPn.2 will load TC to CR2
334 #define TCCR_CR2_F_Msk (1 << 7) // Enable Falling edge on CAPn.2 will load TC to CR2
335 #define TCCR_CR2_I_Msk (1 << 8) // Enable Interrupt on load of CR2
336 #define TCCR_CR3_R_Msk (1 << 9) // Enable Rising edge on CAPn.3 will load TC to CR3
337 #define TCCR_CR3_F_Msk (1 << 10) // Enable Falling edge on CAPn.3 will load TC to CR3
338 #define TCCR_CR3_I_Msk (1 << 11) // Enable Interrupt on load of CR3
339 
340 /** @brief Timer (TIM) register structure definition */
341 typedef struct
342 {
343  __IO uint32_t IR;
344  __IO uint32_t TCR;
345  __IO uint32_t TC;
346  __IO uint32_t PR;
347  __IO uint32_t PC;
348  __IO uint32_t MCR;
349  __IO uint32_t MR0;
350  __IO uint32_t MR1;
351  __IO uint32_t MR2;
352  __IO uint32_t MR3;
353  __IO uint32_t CCR;
354  __I uint32_t CR0;
355  __I uint32_t CR1;
356  uint32_t RESERVED0[2];
357  __IO uint32_t EMR;
358  uint32_t RESERVED1[12];
359  __IO uint32_t CTCR;
360 } LPC_TIM_TypeDef;
361 
362 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
363 // PWM Control Register Bit Definitions
364 #define PWMCR_ENABLE_Msk (1 << 0)
365 #define PWMCR_RESET_Msk (1 << 1)
366 /** @brief Pulse-Width Modulation (PWM) register structure definition */
367 typedef struct
368 {
369  __IO uint32_t IR;
370  __IO uint32_t TCR;
371  __IO uint32_t TC;
372  __IO uint32_t PR;
373  __IO uint32_t PC;
374  __IO uint32_t MCR;
375  __IO uint32_t MR0;
376  __IO uint32_t MR1;
377  __IO uint32_t MR2;
378  __IO uint32_t MR3;
379  __IO uint32_t CCR;
380  __I uint32_t CR0;
381  __I uint32_t CR1;
382  __I uint32_t CR2;
383  __I uint32_t CR3;
384  uint32_t RESERVED0;
385  __IO uint32_t MR4;
386  __IO uint32_t MR5;
387  __IO uint32_t MR6;
388  __IO uint32_t PCR;
389  __IO uint32_t LER;
390  uint32_t RESERVED1[7];
391  __IO uint32_t CTCR;
392 } LPC_PWM_TypeDef;
393 
394 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
395 /** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */
396 typedef struct
397 {
398  union {
399  __I uint8_t RBR;
400  __O uint8_t THR;
401  __IO uint8_t DLL;
402  uint32_t RESERVED0;
403  };
404  union {
405  __IO uint8_t DLM;
406  __IO uint32_t IER;
407  };
408  union {
409  __I uint32_t IIR;
410  __O uint8_t FCR;
411  };
412  __IO uint8_t LCR;
413  uint8_t RESERVED1[7];
414  __I uint8_t LSR;
415  uint8_t RESERVED2[7];
416  __IO uint8_t SCR;
417  uint8_t RESERVED3[3];
418  __IO uint32_t ACR;
419  __IO uint8_t ICR;
420  uint8_t RESERVED4[3];
421  __IO uint8_t FDR;
422  uint8_t RESERVED5[7];
423  __IO uint8_t TER;
424  uint8_t RESERVED6[39];
425  __I uint8_t FIFOLVL;
426 } LPC_UART_TypeDef;
427 
428 /** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
429 typedef struct
430 {
431  union {
432  __I uint8_t RBR;
433  __O uint8_t THR;
434  __IO uint8_t DLL;
435  uint32_t RESERVED0;
436  };
437  union {
438  __IO uint8_t DLM;
439  __IO uint32_t IER;
440  };
441  union {
442  __I uint32_t IIR;
443  __O uint8_t FCR;
444  };
445  __IO uint8_t LCR;
446  uint8_t RESERVED1[7];
447  __I uint8_t LSR;
448  uint8_t RESERVED2[7];
449  __IO uint8_t SCR;
450  uint8_t RESERVED3[3];
451  __IO uint32_t ACR;
452  __IO uint8_t ICR;
453  uint8_t RESERVED4[3];
454  __IO uint8_t FDR;
455  uint8_t RESERVED5[7];
456  __IO uint8_t TER;
457  uint8_t RESERVED6[39];
458  __I uint8_t FIFOLVL;
459 } LPC_UART0_TypeDef;
460 
461 /** @brief Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */
462 typedef struct
463 {
464  union {
465  __I uint8_t RBR;
466  __O uint8_t THR;
467  __IO uint8_t DLL;
468  uint32_t RESERVED0;
469  };
470  union {
471  __IO uint8_t DLM;
472  __IO uint32_t IER;
473  };
474  union {
475  __I uint32_t IIR;
476  __O uint8_t FCR;
477  };
478  __IO uint8_t LCR;
479  uint8_t RESERVED1[3];
480  __IO uint8_t MCR;
481  uint8_t RESERVED2[3];
482  __I uint8_t LSR;
483  uint8_t RESERVED3[3];
484  __I uint8_t MSR;
485  uint8_t RESERVED4[3];
486  __IO uint8_t SCR;
487  uint8_t RESERVED5[3];
488  __IO uint32_t ACR;
489  uint32_t RESERVED6;
490  __IO uint32_t FDR;
491  uint32_t RESERVED7;
492  __IO uint8_t TER;
493  uint8_t RESERVED8[27];
494  __IO uint8_t RS485CTRL;
495  uint8_t RESERVED9[3];
496  __IO uint8_t ADRMATCH;
497  uint8_t RESERVED10[3];
498  __IO uint8_t RS485DLY;
499  uint8_t RESERVED11[3];
500  __I uint8_t FIFOLVL;
501 } LPC_UART1_TypeDef;
502 
503 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
504 /** @brief Serial Peripheral Interface (SPI) register structure definition */
505 typedef struct
506 {
507  __IO uint32_t SPCR;
508  __I uint32_t SPSR;
509  __IO uint32_t SPDR;
510  __IO uint32_t SPCCR;
511  uint32_t RESERVED0[3];
512  __IO uint32_t SPINT;
513 } LPC_SPI_TypeDef;
514 
515 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
516 /** @brief Synchronous Serial Communication (SSP) register structure definition */
517 typedef struct
518 {
519  __IO uint32_t CR0;
520  __IO uint32_t CR1;
521  __IO uint32_t DR;
522  __I uint32_t SR;
523  __IO uint32_t CPSR;
524  __IO uint32_t IMSC;
525  __IO uint32_t RIS;
526  __IO uint32_t MIS;
527  __IO uint32_t ICR;
528  __IO uint32_t DMACR;
529 } LPC_SSP_TypeDef;
530 
531 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
532 /** @brief Inter-Integrated Circuit (I2C) register structure definition */
533 typedef struct
534 {
535  __IO uint32_t I2CONSET;
536  __I uint32_t I2STAT;
537  __IO uint32_t I2DAT;
538  __IO uint32_t I2ADR0;
539  __IO uint32_t I2SCLH;
540  __IO uint32_t I2SCLL;
541  __O uint32_t I2CONCLR;
542  __IO uint32_t MMCTRL;
543  __IO uint32_t I2ADR1;
544  __IO uint32_t I2ADR2;
545  __IO uint32_t I2ADR3;
546  __I uint32_t I2DATA_BUFFER;
547  __IO uint32_t I2MASK0;
548  __IO uint32_t I2MASK1;
549  __IO uint32_t I2MASK2;
550  __IO uint32_t I2MASK3;
551 } LPC_I2C_TypeDef;
552 
553 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
554 /** @brief Inter IC Sound (I2S) register structure definition */
555 typedef struct
556 {
557  __IO uint32_t I2SDAO;
558  __IO uint32_t I2SDAI;
559  __O uint32_t I2STXFIFO;
560  __I uint32_t I2SRXFIFO;
561  __I uint32_t I2SSTATE;
562  __IO uint32_t I2SDMA1;
563  __IO uint32_t I2SDMA2;
564  __IO uint32_t I2SIRQ;
565  __IO uint32_t I2STXRATE;
566  __IO uint32_t I2SRXRATE;
567  __IO uint32_t I2STXBITRATE;
568  __IO uint32_t I2SRXBITRATE;
569  __IO uint32_t I2STXMODE;
570  __IO uint32_t I2SRXMODE;
571 } LPC_I2S_TypeDef;
572 
573 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
574 /** @brief Repetitive Interrupt Timer (RIT) register structure definition */
575 typedef struct
576 {
577  __IO uint32_t RICOMPVAL;
578  __IO uint32_t RIMASK;
579  __IO uint8_t RICTRL;
580  uint8_t RESERVED0[3];
581  __IO uint32_t RICOUNTER;
582 } LPC_RIT_TypeDef;
583 
584 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
585 /** @brief Real-Time Clock (RTC) register structure definition */
586 typedef struct
587 {
588  __IO uint8_t ILR;
589  uint8_t RESERVED0[7];
590  __IO uint8_t CCR;
591  uint8_t RESERVED1[3];
592  __IO uint8_t CIIR;
593  uint8_t RESERVED2[3];
594  __IO uint8_t AMR;
595  uint8_t RESERVED3[3];
596  __I uint32_t CTIME0;
597  __I uint32_t CTIME1;
598  __I uint32_t CTIME2;
599  __IO uint8_t SEC;
600  uint8_t RESERVED4[3];
601  __IO uint8_t MIN;
602  uint8_t RESERVED5[3];
603  __IO uint8_t HOUR;
604  uint8_t RESERVED6[3];
605  __IO uint8_t DOM;
606  uint8_t RESERVED7[3];
607  __IO uint8_t DOW;
608  uint8_t RESERVED8[3];
609  __IO uint16_t DOY;
610  uint16_t RESERVED9;
611  __IO uint8_t MONTH;
612  uint8_t RESERVED10[3];
613  __IO uint16_t YEAR;
614  uint16_t RESERVED11;
615  __IO uint32_t CALIBRATION;
616  __IO uint32_t GPREG0;
617  __IO uint32_t GPREG1;
618  __IO uint32_t GPREG2;
619  __IO uint32_t GPREG3;
620  __IO uint32_t GPREG4;
621  __IO uint8_t RTC_AUXEN;
622  uint8_t RESERVED12[3];
623  __IO uint8_t RTC_AUX;
624  uint8_t RESERVED13[3];
625  __IO uint8_t ALSEC;
626  uint8_t RESERVED14[3];
627  __IO uint8_t ALMIN;
628  uint8_t RESERVED15[3];
629  __IO uint8_t ALHOUR;
630  uint8_t RESERVED16[3];
631  __IO uint8_t ALDOM;
632  uint8_t RESERVED17[3];
633  __IO uint8_t ALDOW;
634  uint8_t RESERVED18[3];
635  __IO uint16_t ALDOY;
636  uint16_t RESERVED19;
637  __IO uint8_t ALMON;
638  uint8_t RESERVED20[3];
639  __IO uint16_t ALYEAR;
640  uint16_t RESERVED21;
641 } LPC_RTC_TypeDef;
642 
643 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
644 /** @brief Watchdog Timer (WDT) register structure definition */
645 typedef struct
646 {
647  __IO uint8_t WDMOD;
648  uint8_t RESERVED0[3];
649  __IO uint32_t WDTC;
650  __O uint8_t WDFEED;
651  uint8_t RESERVED1[3];
652  __I uint32_t WDTV;
653  __IO uint32_t WDCLKSEL;
654 } LPC_WDT_TypeDef;
655 
656 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
657 /** @brief Analog-to-Digital Converter (ADC) register structure definition */
658 typedef struct
659 {
660  __IO uint32_t ADCR;
661  __IO uint32_t ADGDR;
662  uint32_t RESERVED0;
663  __IO uint32_t ADINTEN;
664  __I uint32_t ADDR0;
665  __I uint32_t ADDR1;
666  __I uint32_t ADDR2;
667  __I uint32_t ADDR3;
668  __I uint32_t ADDR4;
669  __I uint32_t ADDR5;
670  __I uint32_t ADDR6;
671  __I uint32_t ADDR7;
672  __I uint32_t ADSTAT;
673  __IO uint32_t ADTRM;
674 } LPC_ADC_TypeDef;
675 
676 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
677 /** @brief Digital-to-Analog Converter (DAC) register structure definition */
678 typedef struct
679 {
680  __IO uint32_t DACR;
681  __IO uint32_t DACCTRL;
682  __IO uint16_t DACCNTVAL;
683 } LPC_DAC_TypeDef;
684 
685 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
686 /** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
687 typedef struct
688 {
689  __I uint32_t MCCON;
690  __O uint32_t MCCON_SET;
691  __O uint32_t MCCON_CLR;
692  __I uint32_t MCCAPCON;
693  __O uint32_t MCCAPCON_SET;
694  __O uint32_t MCCAPCON_CLR;
695  __IO uint32_t MCTIM0;
696  __IO uint32_t MCTIM1;
697  __IO uint32_t MCTIM2;
698  __IO uint32_t MCPER0;
699  __IO uint32_t MCPER1;
700  __IO uint32_t MCPER2;
701  __IO uint32_t MCPW0;
702  __IO uint32_t MCPW1;
703  __IO uint32_t MCPW2;
704  __IO uint32_t MCDEADTIME;
705  __IO uint32_t MCCCP;
706  __IO uint32_t MCCR0;
707  __IO uint32_t MCCR1;
708  __IO uint32_t MCCR2;
709  __I uint32_t MCINTEN;
710  __O uint32_t MCINTEN_SET;
711  __O uint32_t MCINTEN_CLR;
712  __I uint32_t MCCNTCON;
713  __O uint32_t MCCNTCON_SET;
714  __O uint32_t MCCNTCON_CLR;
715  __I uint32_t MCINTFLAG;
716  __O uint32_t MCINTFLAG_SET;
717  __O uint32_t MCINTFLAG_CLR;
718  __O uint32_t MCCAP_CLR;
719 } LPC_MCPWM_TypeDef;
720 
721 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
722 /** @brief Quadrature Encoder Interface (QEI) register structure definition */
723 typedef struct
724 {
725  __O uint32_t QEICON;
726  __I uint32_t QEISTAT;
727  __IO uint32_t QEICONF;
728  __I uint32_t QEIPOS;
729  __IO uint32_t QEIMAXPOS;
730  __IO uint32_t CMPOS0;
731  __IO uint32_t CMPOS1;
732  __IO uint32_t CMPOS2;
733  __I uint32_t INXCNT;
734  __IO uint32_t INXCMP;
735  __IO uint32_t QEILOAD;
736  __I uint32_t QEITIME;
737  __I uint32_t QEIVEL;
738  __I uint32_t QEICAP;
739  __IO uint32_t VELCOMP;
740  __IO uint32_t FILTER;
741  uint32_t RESERVED0[998];
742  __O uint32_t QEIIEC;
743  __O uint32_t QEIIES;
744  __I uint32_t QEIINTSTAT;
745  __I uint32_t QEIIE;
746  __O uint32_t QEICLR;
747  __O uint32_t QEISET;
748 } LPC_QEI_TypeDef;
749 
750 /*------------- Controller Area Network (CAN) --------------------------------*/
751 /** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
752 typedef struct
753 {
754  __IO uint32_t mask[512]; /* ID Masks */
755 } LPC_CANAF_RAM_TypeDef;
756 
757 /** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
758 typedef struct /* Acceptance Filter Registers */
759 {
760  __IO uint32_t AFMR;
761  __IO uint32_t SFF_sa;
762  __IO uint32_t SFF_GRP_sa;
763  __IO uint32_t EFF_sa;
764  __IO uint32_t EFF_GRP_sa;
765  __IO uint32_t ENDofTable;
766  __I uint32_t LUTerrAd;
767  __I uint32_t LUTerr;
768  __IO uint32_t FCANIE;
769  __IO uint32_t FCANIC0;
770  __IO uint32_t FCANIC1;
771 } LPC_CANAF_TypeDef;
772 
773 /** @brief Controller Area Network Central (CANCR) register structure definition */
774 typedef struct /* Central Registers */
775 {
776  __I uint32_t CANTxSR;
777  __I uint32_t CANRxSR;
778  __I uint32_t CANMSR;
779 } LPC_CANCR_TypeDef;
780 
781 /** @brief Controller Area Network Controller (CAN) register structure definition */
782 typedef struct /* Controller Registers */
783 {
784  __IO uint32_t MOD;
785  __O uint32_t CMR;
786  __IO uint32_t GSR;
787  __I uint32_t ICR;
788  __IO uint32_t IER;
789  __IO uint32_t BTR;
790  __IO uint32_t EWL;
791  __I uint32_t SR;
792  __IO uint32_t RFS;
793  __IO uint32_t RID;
794  __IO uint32_t RDA;
795  __IO uint32_t RDB;
796  __IO uint32_t TFI1;
797  __IO uint32_t TID1;
798  __IO uint32_t TDA1;
799  __IO uint32_t TDB1;
800  __IO uint32_t TFI2;
801  __IO uint32_t TID2;
802  __IO uint32_t TDA2;
803  __IO uint32_t TDB2;
804  __IO uint32_t TFI3;
805  __IO uint32_t TID3;
806  __IO uint32_t TDA3;
807  __IO uint32_t TDB3;
808 } LPC_CAN_TypeDef;
809 
810 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
811 /** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
812 typedef struct /* Common Registers */
813 {
814  __I uint32_t DMACIntStat;
815  __I uint32_t DMACIntTCStat;
816  __O uint32_t DMACIntTCClear;
817  __I uint32_t DMACIntErrStat;
818  __O uint32_t DMACIntErrClr;
819  __I uint32_t DMACRawIntTCStat;
820  __I uint32_t DMACRawIntErrStat;
821  __I uint32_t DMACEnbldChns;
822  __IO uint32_t DMACSoftBReq;
823  __IO uint32_t DMACSoftSReq;
824  __IO uint32_t DMACSoftLBReq;
825  __IO uint32_t DMACSoftLSReq;
826  __IO uint32_t DMACConfig;
827  __IO uint32_t DMACSync;
828 } LPC_GPDMA_TypeDef;
829 
830 /** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
831 typedef struct /* Channel Registers */
832 {
833  __IO uint32_t DMACCSrcAddr;
834  __IO uint32_t DMACCDestAddr;
835  __IO uint32_t DMACCLLI;
836  __IO uint32_t DMACCControl;
837  __IO uint32_t DMACCConfig;
838 } LPC_GPDMACH_TypeDef;
839 
840 /*------------- Universal Serial Bus (USB) -----------------------------------*/
841 /** @brief Universal Serial Bus (USB) register structure definition */
842 typedef struct
843 {
844  __I uint32_t HcRevision; /* USB Host Registers */
845  __IO uint32_t HcControl;
846  __IO uint32_t HcCommandStatus;
847  __IO uint32_t HcInterruptStatus;
848  __IO uint32_t HcInterruptEnable;
849  __IO uint32_t HcInterruptDisable;
850  __IO uint32_t HcHCCA;
851  __I uint32_t HcPeriodCurrentED;
852  __IO uint32_t HcControlHeadED;
853  __IO uint32_t HcControlCurrentED;
854  __IO uint32_t HcBulkHeadED;
855  __IO uint32_t HcBulkCurrentED;
856  __I uint32_t HcDoneHead;
857  __IO uint32_t HcFmInterval;
858  __I uint32_t HcFmRemaining;
859  __I uint32_t HcFmNumber;
860  __IO uint32_t HcPeriodicStart;
861  __IO uint32_t HcLSTreshold;
862  __IO uint32_t HcRhDescriptorA;
863  __IO uint32_t HcRhDescriptorB;
864  __IO uint32_t HcRhStatus;
865  __IO uint32_t HcRhPortStatus1;
866  __IO uint32_t HcRhPortStatus2;
867  uint32_t RESERVED0[40];
868  __I uint32_t Module_ID;
869 
870  __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
871  __IO uint32_t OTGIntEn;
872  __O uint32_t OTGIntSet;
873  __O uint32_t OTGIntClr;
874  __IO uint32_t OTGStCtrl;
875  __IO uint32_t OTGTmr;
876  uint32_t RESERVED1[58];
877 
878  __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
879  __IO uint32_t USBDevIntEn;
880  __O uint32_t USBDevIntClr;
881  __O uint32_t USBDevIntSet;
882 
883  __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
884  __I uint32_t USBCmdData;
885 
886  __I uint32_t USBRxData; /* USB Device Transfer Registers */
887  __O uint32_t USBTxData;
888  __I uint32_t USBRxPLen;
889  __O uint32_t USBTxPLen;
890  __IO uint32_t USBCtrl;
891  __O uint32_t USBDevIntPri;
892 
893  __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
894  __IO uint32_t USBEpIntEn;
895  __O uint32_t USBEpIntClr;
896  __O uint32_t USBEpIntSet;
897  __O uint32_t USBEpIntPri;
898 
899  __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
900  __O uint32_t USBEpInd;
901  __IO uint32_t USBMaxPSize;
902 
903  __I uint32_t USBDMARSt; /* USB Device DMA Registers */
904  __O uint32_t USBDMARClr;
905  __O uint32_t USBDMARSet;
906  uint32_t RESERVED2[9];
907  __IO uint32_t USBUDCAH;
908  __I uint32_t USBEpDMASt;
909  __O uint32_t USBEpDMAEn;
910  __O uint32_t USBEpDMADis;
911  __I uint32_t USBDMAIntSt;
912  __IO uint32_t USBDMAIntEn;
913  uint32_t RESERVED3[2];
914  __I uint32_t USBEoTIntSt;
915  __O uint32_t USBEoTIntClr;
916  __O uint32_t USBEoTIntSet;
917  __I uint32_t USBNDDRIntSt;
918  __O uint32_t USBNDDRIntClr;
919  __O uint32_t USBNDDRIntSet;
920  __I uint32_t USBSysErrIntSt;
921  __O uint32_t USBSysErrIntClr;
922  __O uint32_t USBSysErrIntSet;
923  uint32_t RESERVED4[15];
924 
925  union {
926  __I uint32_t I2C_RX; /* USB OTG I2C Registers */
927  __O uint32_t I2C_TX;
928  };
929  __I uint32_t I2C_STS;
930  __IO uint32_t I2C_CTL;
931  __IO uint32_t I2C_CLKHI;
932  __O uint32_t I2C_CLKLO;
933  uint32_t RESERVED5[824];
934 
935  union {
936  __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
937  __IO uint32_t OTGClkCtrl;
938  };
939  union {
940  __I uint32_t USBClkSt;
941  __I uint32_t OTGClkSt;
942  };
943 } LPC_USB_TypeDef;
944 
945 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
946 /** @brief Ethernet Media Access Controller (EMAC) register structure definition */
947 typedef struct
948 {
949  __IO uint32_t MAC1; /* MAC Registers */
950  __IO uint32_t MAC2;
951  __IO uint32_t IPGT;
952  __IO uint32_t IPGR;
953  __IO uint32_t CLRT;
954  __IO uint32_t MAXF;
955  __IO uint32_t SUPP;
956  __IO uint32_t TEST;
957  __IO uint32_t MCFG;
958  __IO uint32_t MCMD;
959  __IO uint32_t MADR;
960  __O uint32_t MWTD;
961  __I uint32_t MRDD;
962  __I uint32_t MIND;
963  uint32_t RESERVED0[2];
964  __IO uint32_t SA0;
965  __IO uint32_t SA1;
966  __IO uint32_t SA2;
967  uint32_t RESERVED1[45];
968  __IO uint32_t Command; /* Control Registers */
969  __I uint32_t Status;
970  __IO uint32_t RxDescriptor;
971  __IO uint32_t RxStatus;
972  __IO uint32_t RxDescriptorNumber;
973  __I uint32_t RxProduceIndex;
974  __IO uint32_t RxConsumeIndex;
975  __IO uint32_t TxDescriptor;
976  __IO uint32_t TxStatus;
977  __IO uint32_t TxDescriptorNumber;
978  __IO uint32_t TxProduceIndex;
979  __I uint32_t TxConsumeIndex;
980  uint32_t RESERVED2[10];
981  __I uint32_t TSV0;
982  __I uint32_t TSV1;
983  __I uint32_t RSV;
984  uint32_t RESERVED3[3];
985  __IO uint32_t FlowControlCounter;
986  __I uint32_t FlowControlStatus;
987  uint32_t RESERVED4[34];
988  __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
989  __IO uint32_t RxFilterWoLStatus;
990  __IO uint32_t RxFilterWoLClear;
991  uint32_t RESERVED5;
992  __IO uint32_t HashFilterL;
993  __IO uint32_t HashFilterH;
994  uint32_t RESERVED6[882];
995  __I uint32_t IntStatus; /* Module Control Registers */
996  __IO uint32_t IntEnable;
997  __O uint32_t IntClear;
998  __O uint32_t IntSet;
999  uint32_t RESERVED7;
1000  __IO uint32_t PowerDown;
1001  uint32_t RESERVED8;
1002  __IO uint32_t Module_ID;
1003 } LPC_EMAC_TypeDef;
1004 
1005 
1006 #if defined ( __CC_ARM )
1007 #pragma no_anon_unions
1008 #endif
1009 
1010 
1011 /******************************************************************************/
1012 /* Peripheral memory map */
1013 /******************************************************************************/
1014 /* Base addresses */
1015 #define LPC_FLASH_BASE (0x00000000UL)
1016 #define LPC_RAM_BASE (0x10000000UL)
1017 #ifdef __LPC17XX_REV00
1018 #define LPC_AHBRAM0_BASE (0x20000000UL)
1019 #define LPC_AHBRAM1_BASE (0x20004000UL)
1020 #else
1021 #define LPC_AHBRAM0_BASE (0x2007C000UL)
1022 #define LPC_AHBRAM1_BASE (0x20080000UL)
1023 #endif
1024 #define LPC_GPIO_BASE (0x2009C000UL)
1025 #define LPC_APB0_BASE (0x40000000UL)
1026 #define LPC_APB1_BASE (0x40080000UL)
1027 #define LPC_AHB_BASE (0x50000000UL)
1028 #define LPC_CM3_BASE (0xE0000000UL)
1029 
1030 /* APB0 peripherals */
1031 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
1032 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
1033 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
1034 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
1035 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
1036 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
1037 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
1038 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
1039 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
1040 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
1041 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
1042 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
1043 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
1044 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
1045 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
1046 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
1047 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
1048 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
1049 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
1050 
1051 /* APB1 peripherals */
1052 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
1053 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
1054 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
1055 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
1056 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
1057 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
1058 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
1059 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
1060 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
1061 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
1062 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
1063 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
1064 
1065 /* AHB peripherals */
1066 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
1067 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
1068 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
1069 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
1070 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
1071 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
1072 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
1073 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
1074 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
1075 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
1076 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
1077 
1078 /* GPIOs */
1079 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
1080 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
1081 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
1082 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
1083 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
1084 
1085 /******************************************************************************/
1086 /* Peripheral declaration */
1087 /******************************************************************************/
1088 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
1089 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
1090 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
1091 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
1092 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
1093 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
1094 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
1095 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
1096 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
1097 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
1098 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
1099 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
1100 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
1101 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
1102 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
1103 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
1104 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
1105 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
1106 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
1107 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
1108 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
1109 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
1110 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
1111 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
1112 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
1113 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
1114 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
1115 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
1116 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
1117 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
1118 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
1119 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
1120 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
1121 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
1122 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
1123 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
1124 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
1125 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
1126 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
1127 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
1128 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
1129 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
1130 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
1131 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
1132 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
1133 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
1134 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
1135 
1136 /**
1137  * @}
1138  */
1139 
1140 #endif // __LPC17xx_H__