LPC17xx.h File Reference

CMSIS Cortex-M3 Core Peripheral Access Layer Header File for NXP LPC17xx Device Series. More...

#include "core_cm3.h"
#include "system_LPC17xx.h"

Include dependency graph for LPC17xx.h:

Go to the source code of this file.

Data Structures
struct	LPC_ADC_TypeDef
	Analog-to-Digital Converter (ADC) register structure definition. More...
struct	LPC_CAN_TypeDef
	Controller Area Network Controller (CAN) register structure definition. More...
struct	LPC_CANAF_RAM_TypeDef
	Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition. More...
struct	LPC_CANAF_TypeDef
	Controller Area Network Acceptance Filter(CANAF) register structure definition. More...
struct	LPC_CANCR_TypeDef
	Controller Area Network Central (CANCR) register structure definition. More...
struct	LPC_DAC_TypeDef
	Digital-to-Analog Converter (DAC) register structure definition. More...
struct	LPC_EMAC_TypeDef
	Ethernet Media Access Controller (EMAC) register structure definition. More...
struct	LPC_GPDMA_TypeDef
	General Purpose Direct Memory Access (GPDMA) register structure definition. More...
struct	LPC_GPDMACH_TypeDef
	General Purpose Direct Memory Access Channel (GPDMACH) register structure definition. More...
struct	LPC_GPIO_TypeDef
	General Purpose Input/Output (GPIO) register structure definition. More...
struct	LPC_GPIOINT_TypeDef
	General Purpose Input/Output interrupt (GPIOINT) register structure definition. More...
struct	LPC_I2C_TypeDef
	Inter-Integrated Circuit (I2C) register structure definition. More...
struct	LPC_I2S_TypeDef
	Inter IC Sound (I2S) register structure definition. More...
struct	LPC_MCPWM_TypeDef
	Motor Control Pulse-Width Modulation (MCPWM) register structure definition. More...
struct	LPC_PINCON_TypeDef
	Pin Connect Block (PINCON) register structure definition. More...
struct	LPC_PWM_TypeDef
	Pulse-Width Modulation (PWM) register structure definition. More...
struct	LPC_QEI_TypeDef
	Quadrature Encoder Interface (QEI) register structure definition. More...
struct	LPC_RIT_TypeDef
	Repetitive Interrupt Timer (RIT) register structure definition. More...
struct	LPC_RTC_TypeDef
	Real-Time Clock (RTC) register structure definition. More...
struct	LPC_SC_TypeDef
	System Control (SC) register structure definition. More...
struct	LPC_SPI_TypeDef
	Serial Peripheral Interface (SPI) register structure definition. More...
struct	LPC_SSP_TypeDef
	Synchronous Serial Communication (SSP) register structure definition. More...
struct	LPC_TIM_TypeDef
	Timer (TIM) register structure definition. More...
struct	LPC_UART0_TypeDef
	Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition. More...
struct	LPC_UART1_TypeDef
	Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition. More...
struct	LPC_UART_TypeDef
	Universal Asynchronous Receiver Transmitter (UART) register structure definition. More...
struct	LPC_USB_TypeDef
	Universal Serial Bus (USB) register structure definition. More...
struct	LPC_WDT_TypeDef
	Watchdog Timer (WDT) register structure definition. More...

Macros
#define	__MPU_PRESENT   1
#define	__NVIC_PRIO_BITS   5
#define	__Vendor_SysTickConfig   0
#define	i_ARCH   CM3
#define	i_MCU_MODEL   1761
#define	LPC_ADC   ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define	LPC_ADC_BASE   (LPC_APB0_BASE + 0x34000)
#define	LPC_AHB_BASE   (0x50000000UL)
#define	LPC_AHBRAM0_BASE   (0x2007C000UL)
#define	LPC_AHBRAM1_BASE   (0x20080000UL)
#define	LPC_APB0_BASE   (0x40000000UL)
#define	LPC_APB1_BASE   (0x40080000UL)
#define	LPC_CAN1   ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
#define	LPC_CAN1_BASE   (LPC_APB0_BASE + 0x44000)
#define	LPC_CAN2   ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
#define	LPC_CAN2_BASE   (LPC_APB0_BASE + 0x48000)
#define	LPC_CANAF   ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
#define	LPC_CANAF_BASE   (LPC_APB0_BASE + 0x3C000)
#define	LPC_CANAF_RAM   ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
#define	LPC_CANAF_RAM_BASE   (LPC_APB0_BASE + 0x38000)
#define	LPC_CANCR   ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
#define	LPC_CANCR_BASE   (LPC_APB0_BASE + 0x40000)
#define	LPC_CM3_BASE   (0xE0000000UL)
#define	LPC_DAC   ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
#define	LPC_DAC_BASE   (LPC_APB1_BASE + 0x0C000)
#define	LPC_EMAC   ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
#define	LPC_EMAC_BASE   (LPC_AHB_BASE + 0x00000)
#define	LPC_FLASH_BASE   (0x00000000UL)
#define	LPC_GPDMA   ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
#define	LPC_GPDMA_BASE   (LPC_AHB_BASE + 0x04000)
#define	LPC_GPDMACH0   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
#define	LPC_GPDMACH0_BASE   (LPC_AHB_BASE + 0x04100)
#define	LPC_GPDMACH1   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
#define	LPC_GPDMACH1_BASE   (LPC_AHB_BASE + 0x04120)
#define	LPC_GPDMACH2   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
#define	LPC_GPDMACH2_BASE   (LPC_AHB_BASE + 0x04140)
#define	LPC_GPDMACH3   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
#define	LPC_GPDMACH3_BASE   (LPC_AHB_BASE + 0x04160)
#define	LPC_GPDMACH4   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
#define	LPC_GPDMACH4_BASE   (LPC_AHB_BASE + 0x04180)
#define	LPC_GPDMACH5   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
#define	LPC_GPDMACH5_BASE   (LPC_AHB_BASE + 0x041A0)
#define	LPC_GPDMACH6   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
#define	LPC_GPDMACH6_BASE   (LPC_AHB_BASE + 0x041C0)
#define	LPC_GPDMACH7   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
#define	LPC_GPDMACH7_BASE   (LPC_AHB_BASE + 0x041E0)
#define	LPC_GPIO0   ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
#define	LPC_GPIO0_BASE   (LPC_GPIO_BASE + 0x00000)
#define	LPC_GPIO1   ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
#define	LPC_GPIO1_BASE   (LPC_GPIO_BASE + 0x00020)
#define	LPC_GPIO2   ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
#define	LPC_GPIO2_BASE   (LPC_GPIO_BASE + 0x00040)
#define	LPC_GPIO3   ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
#define	LPC_GPIO3_BASE   (LPC_GPIO_BASE + 0x00060)
#define	LPC_GPIO4   ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
#define	LPC_GPIO4_BASE   (LPC_GPIO_BASE + 0x00080)
#define	LPC_GPIO_BASE   (0x2009C000UL)
#define	LPC_GPIOINT   ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
#define	LPC_GPIOINT_BASE   (LPC_APB0_BASE + 0x28080)
#define	LPC_I2C0   ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
#define	LPC_I2C0_BASE   (LPC_APB0_BASE + 0x1C000)
#define	LPC_I2C1   ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
#define	LPC_I2C1_BASE   (LPC_APB0_BASE + 0x5C000)
#define	LPC_I2C2   ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
#define	LPC_I2C2_BASE   (LPC_APB1_BASE + 0x20000)
#define	LPC_I2S   ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
#define	LPC_I2S_BASE   (LPC_APB1_BASE + 0x28000)
#define	LPC_MCPWM   ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
#define	LPC_MCPWM_BASE   (LPC_APB1_BASE + 0x38000)
#define	LPC_PINCON   ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
#define	LPC_PINCON_BASE   (LPC_APB0_BASE + 0x2C000)
#define	LPC_PWM1   ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
#define	LPC_PWM1_BASE   (LPC_APB0_BASE + 0x18000)
#define	LPC_QEI   ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
#define	LPC_QEI_BASE   (LPC_APB1_BASE + 0x3C000)
#define	LPC_RAM_BASE   (0x10000000UL)
#define	LPC_RIT   ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
#define	LPC_RIT_BASE   (LPC_APB1_BASE + 0x30000)
#define	LPC_RTC   ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
#define	LPC_RTC_BASE   (LPC_APB0_BASE + 0x24000)
#define	LPC_SC   ((LPC_SC_TypeDef *) LPC_SC_BASE )
#define	LPC_SC_BASE   (LPC_APB1_BASE + 0x7C000)
#define	LPC_SPI   ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
#define	LPC_SPI_BASE   (LPC_APB0_BASE + 0x20000)
#define	LPC_SSP0   ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
#define	LPC_SSP0_BASE   (LPC_APB1_BASE + 0x08000)
#define	LPC_SSP1   ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
#define	LPC_SSP1_BASE   (LPC_APB0_BASE + 0x30000)
#define	LPC_TIM0   ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
#define	LPC_TIM0_BASE   (LPC_APB0_BASE + 0x04000)
#define	LPC_TIM1   ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
#define	LPC_TIM1_BASE   (LPC_APB0_BASE + 0x08000)
#define	LPC_TIM2   ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
#define	LPC_TIM2_BASE   (LPC_APB1_BASE + 0x10000)
#define	LPC_TIM3   ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
#define	LPC_TIM3_BASE   (LPC_APB1_BASE + 0x14000)
#define	LPC_UART0   ((LPC_UART_TypeDef *) LPC_UART0_BASE )
#define	LPC_UART0_BASE   (LPC_APB0_BASE + 0x0C000)
#define	LPC_UART1   ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
#define	LPC_UART1_BASE   (LPC_APB0_BASE + 0x10000)
#define	LPC_UART2   ((LPC_UART_TypeDef *) LPC_UART2_BASE )
#define	LPC_UART2_BASE   (LPC_APB1_BASE + 0x18000)
#define	LPC_UART3   ((LPC_UART_TypeDef *) LPC_UART3_BASE )
#define	LPC_UART3_BASE   (LPC_APB1_BASE + 0x1C000)
#define	LPC_USB   ((LPC_USB_TypeDef *) LPC_USB_BASE )
#define	LPC_USB_BASE   (LPC_AHB_BASE + 0x0C000)
#define	LPC_WDT   ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
#define	LPC_WDT_BASE   (LPC_APB0_BASE + 0x00000)
#define	PWMCR_ENABLE_Msk   (1 << 0)
#define	PWMCR_RESET_Msk   (1 << 1)
#define	PWMIR_MR0I_Msk   (1 << 0)
#define	PWMIR_MR1I_Msk   (1 << 1)
#define	PWMIR_MR2I_Msk   (1 << 2)
#define	PWMIR_MR3I_Msk   (1 << 3)
#define	PWMIR_MR4I_Msk   (1 << 8)
#define	PWMIR_MR5I_Msk   (1 << 9)
#define	PWMIR_MR6I_Msk   (1 << 10)
#define	PWMIR_Msk   (0x070F)
#define	TCCR_CR0_F_Msk   (1 << 1)
#define	TCCR_CR0_I_Msk   (1 << 2)
#define	TCCR_CR0_R_Msk   (1 << 0)
#define	TCCR_CR1_F_Msk   (1 << 4)
#define	TCCR_CR1_I_Msk   (1 << 5)
#define	TCCR_CR1_R_Msk   (1 << 3)
#define	TCCR_CR2_F_Msk   (1 << 7)
#define	TCCR_CR2_I_Msk   (1 << 8)
#define	TCCR_CR2_R_Msk   (1 << 6)
#define	TCCR_CR3_F_Msk   (1 << 10)
#define	TCCR_CR3_I_Msk   (1 << 11)
#define	TCCR_CR3_R_Msk   (1 << 9)
#define	TCR_ENABLE_Msk   (1 << 0)
#define	TCR_RESET_Msk   (1 << 1)
#define	TIR_CR0I_Msk   (1 << 4)
#define	TIR_CR1I_Msk   (1 << 5)
#define	TIR_CR2I_Msk   (1 << 6)
#define	TIR_CR3I_Msk   (1 << 7)
#define	TIR_MR0I_Msk   (1 << 0)
#define	TIR_MR1I_Msk   (1 << 1)
#define	TIR_MR2I_Msk   (1 << 2)
#define	TIR_MR3I_Msk   (1 << 3)
#define	TMCR_MR0_I_Msk   (1 << 0)
#define	TMCR_MR0_R_Msk   (1 << 1)
#define	TMCR_MR0_S_Msk   (1 << 2)
#define	TMCR_MR1_I_Msk   (1 << 3)
#define	TMCR_MR1_R_Msk   (1 << 4)
#define	TMCR_MR1_S_Msk   (1 << 5)
#define	TMCR_MR2_I_Msk   (1 << 6)
#define	TMCR_MR2_R_Msk   (1 << 7)
#define	TMCR_MR2_S_Msk   (1 << 8)
#define	TMCR_MR3_I_Msk   (1 << 9)
#define	TMCR_MR3_R_Msk   (1 << 10)
#define	TMCR_MR3_S_Msk   (1 << 11)

Typedefs
typedef enum IRQn	IRQn_Type
	IRQ interrupt source definition.

Enumerations
enum	IRQn {   NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2,   SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,   TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,   UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,   CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,   CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,   I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,   NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2,   SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,   TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,   UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,   CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,   CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,   I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,   NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,   UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,   SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,   TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,   UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,   CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,   CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,   I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,   NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,   UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,   SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,   TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,   UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,   CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,   CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,   I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,   NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2,   SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,   TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,   UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,   CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,   CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,   I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,   NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,   UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,   SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,   TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,   UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,   CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,   CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,   I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,   NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,   SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,   WDT_IRQn = 0, TIMER0_IRQn = 1, TIMER1_IRQn = 2, TIMER2_IRQn = 3,   TIMER3_IRQn = 4, UART0_IRQn = 5, UART1_IRQn = 6, UART2_IRQn = 7,   UART3_IRQn = 8, PWM1_IRQn = 9, I2C0_IRQn = 10, I2C1_IRQn = 11,   I2C2_IRQn = 12, SPI_IRQn = 13, SSP0_IRQn = 14, SSP1_IRQn = 15,   PLL0_IRQn = 16, RTC_IRQn = 17, EINT0_IRQn = 18, EINT1_IRQn = 19,   EINT2_IRQn = 20, EINT3_IRQn = 21, ADC_IRQn = 22, BOD_IRQn = 23,   USB_IRQn = 24, CAN_IRQn = 25, DMA_IRQn = 26, I2S_IRQn = 27,   ENET_IRQn = 28, RIT_IRQn = 29, MCPWM_IRQn = 30, QEI_IRQn = 31,   PLL1_IRQn = 32, USBActivity_IRQn = 33, CANActivity_IRQn = 34, WDT_IRQn = 0,   PROGRAMM_INT_IRQn = 1, ARM_CORE_ICE_RX_IRQn = 2, ARM_CORE_ICE_TX_IRQn = 3, TIMER0_IRQn = 4,   TIMER1_IRQn = 5, UART0_IRQn = 6, UART1_IRQn = 7, PWM_IRQn = 8,   PWM0_IRQn = 8, I2C_IRQn = 9, I2C0_IRQn = 9, SPI_IRQn = 10,   SPI0_IRQn = 10, SSP0_IRQn = 10, SPI1_IRQn = 11, SSP1_IRQn = 11,   PLL0_IRQn = 12, RTC_IRQn = 13, EINT0_IRQn = 14, EINT1_IRQn = 15,   EINT2_IRQn = 16, EINT3_IRQn = 17, ADC_IRQn = 18, CAN1_TX = 20,   CAN2_TX_IRQn = 21, CAN3_TX_IRQn = 22, CAN4_TX_IRQn = 23, RESERVE_23_IRQn = 24,   RESERVE_24_IRQn = 25, CAN1_RX_IRQn = 26, CAN2_RX_IRQn = 27, CAN3_RX_IRQn = 28,   CAN4_RX_IRQn = 29 }
	IRQ interrupt source definition. More...

Detailed Description

CMSIS Cortex-M3 Core Peripheral Access Layer Header File for NXP LPC17xx Device Series.

Version

: V1.09

Date

: 25. July. 2011

Note

Copyright (C) 2009 ARM Limited. All rights reserved.

ARM Limited (ARM) is supplying this software for use with Cortex-M processor based microcontrollers. This file can be freely distributed within development tools that are supporting such ARM based processors.

THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

Definition in file LPC17xx.h.

Macro Definition Documentation

#define i_ARCH   CM3

Definition at line 33 of file LPC17xx.h.

#define i_MCU_MODEL   1761

Definition at line 31 of file LPC17xx.h.