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LPC2xxx.h
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1 /*
2  * CMSIS2000
3  * CMSIS-like sources for LPC2xxx series MCUs
4  *
5  * (C) Copyright 2011-2012, Dmitriy Cherepanov, All Rights Reserved
6  *
7  * Version: 0.0.7
8  * Date of the Last Update: 2013-03-04
9  *
10  * Permission is hereby granted, free of charge, to any person obtaining a copy
11  * of this software and associated documentation files (the "Software"), to
12  * deal in the Software without restriction, including without limitation the
13  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
14  * sell copies of the Software, and to permit persons to whom the Software is
15  * furnished to do so, subject to the following conditions:
16  *
17  * The above copyright notice and this permission notice shall be included in
18  * all copies or substantial portions of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
23  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26  * IN THE SOFTWARE.
27  *
28  * Do not be lasy! For the latest version see http://irtos.sourceforge.net .
29  *
30  *
31 #*/
32 
33 #ifndef _ARCH_ARM_NXP_LPC2XXX_CMSIS_H_
34 #define _ARCH_ARM_NXP_LPC2XXX_CMSIS_H_ 1
35 /*-----------Документация Doxygen -- Doxygen documentation -----------------*/
36 /** \file
37  *\if russian_lng
38  * Перефирийные регистры в LPC in CMSIS like style
39  *\else
40  * APB(ARM Peripheral Bus) peripheries registers CMSIS like style
41  *\endif
42  * \author Dmitriy Cherepanov
43  * \date 2010
44  * \date 2012
45  * \ingroup LPC2xxx_System
46  */
47 /**
48  *\if russian_lng
49  * \defgroup reg_addresses_LPC2000 Адреса перефирийных регистров в LPC
50  *\else
51  * \defgroup reg_addresses_LPC2000 APB(ARM Peripheral Bus) peripheries registers addresses
52  *\endif
53  * \ingroup LPC2xxx_System
54  */
55 
56 
57 /*-------------MCU NUMBER --------------------------------------------------*/
58 /*if MCU has suffix 01 (for ex 2106/01) then is has new VIC and may be other modules */
59 #ifndef i_MCU_MODEL
60  #include "mcu_id.h"/* !!! THIS FILE MUST DEFINE MCU_ID*/
61  #ifndef i_MCU_MODEL
62  #define i_MCU_MODEL 2101
63  #endif
64 #endif
65 /*------ МАКРОСЫ И ОПРЕДЕЛЕНИЯ - MACROSES ------------------------------------*/
66 /** \addtogroup LPC2xxx_System_IRQ LPC2xxx IRQ Numbers
67  * \ingroup LPC2xxx_System
68  * @{
69  */
70 
71 typedef enum IRQn {
72  WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
73  PROGRAMM_INT_IRQn = 1,
74  ARM_CORE_ICE_RX_IRQn = 2,
75  ARM_CORE_ICE_TX_IRQn = 3,
76  TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
77  TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
78  UART0_IRQn = 6, /*!< UART0 Interrupt */
79  UART1_IRQn = 7, /*!< UART1 Interrupt */
80  PWM_IRQn = 8, /*!< PWM Interrupt */
81  PWM0_IRQn = 8, /*!< PWM0 Interrupt */
82  I2C_IRQn = 9, /*!< I2C Interrupt */
83  I2C0_IRQn = 9, /*!< I2C0 Interrupt */
84  SPI_IRQn = 10, /*!< SPI Interrupt */
85  SPI0_IRQn = 10, /*!< SPI0 Interrupt */
86  SSP0_IRQn = 10, /*!< SSP0 Interrupt */
87  SPI1_IRQn = 11, /*!< SPI1 Interrupt */
88  SSP1_IRQn = 11, /*!< SSP1 Interrupt */
89  PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
90  RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
91  EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
92  EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
93  EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
94  EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
95  ADC_IRQn = 18, /*!< A/D Converter Interrupt */
96 #if (i_MCU_MODEL >= 2300)
97  I2C1_IRQn = 19, /*!< I2C1 Interrupt */
98  BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
99  ENET_IRQn = 21, /*!< Ethernet Interrupt */
100  USB_IRQn = 22, /*!< USB Interrupt */
101  CAN_IRQn = 23, /*!< CAN Interrupt */
102  MCI_IRQn = 24, /*!< USB Interrupt */
103  DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
104 //#if (i_MCU_MODEL >= 2400)
105  /* for lpc 24xx*/
106  TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
107  TIMER3_IRQn = 27, /*!< Timer3 */
108  UART2_IRQn = 28, /*!< UART2 Interrupt */
109  UART3_IRQn = 29, /*!< UART3 Interrupt */
110  I2C2_IRQn = 30, /*!< I2C2 Interrupt */
111  I2S_IRQn = 31, /*!< I2S Interrupt */
112 //#endif
113 #else /*(i_MCU_MODEL < 2300)*/
114  CAN1_TX = 20,
115  CAN2_TX_IRQn = 21,
116  CAN3_TX_IRQn = 22,
117  CAN4_TX_IRQn = 23,
118  RESERVE_23_IRQn = 24,
119  RESERVE_24_IRQn = 25,
120  CAN1_RX_IRQn = 26,
121  CAN2_RX_IRQn = 27,
122  CAN3_RX_IRQn = 28,
123  CAN4_RX_IRQn = 29
124 #endif
125 } IRQn_Type;
126 /** @}
127  */
128 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
129 #define __MPU_PRESENT 0 /*!< MPU present or not */
130 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
131 #define __Vendor_SysTickConfig 1 /*!< Set to 1 if different SysTick Config is used */
132 
133 
134 #include "core_7tdmi.h" /* ARM7-TDMI processor and core peripherals */
135 #include "system_LPC2xxx.h" /* System Header */
136 
137 #if defined ( __CC_ARM )
138 #pragma anon_unions
139 #endif
140 
141 /** \addtogroup reg_addresses_LPC2000
142  * @{
143  */
144 /*-------------Vectored Interrupt Controller(VIC)-----------------------------*/
145 // Vectored Interrupt Controller Registers (VIC)
146 #if i_MCU_MODEL >= 2300
147  #define VIC_SIZE 32
148 #else
149  #define VIC_SIZE 16
150 #endif
151 typedef struct
152 {
153  __I uint32_t IRQStatus; /**< IRQ Status Register */
154  __I uint32_t FIQStatus; /**< FIQ Status Register */
155  __I uint32_t RawIntr; /**< Raw Interrupt Status Register */
156  __IO uint32_t IntSelect; /**< Interrupt Select Register */
157  __IO uint32_t IntEnable; /**< Interrupt Enable Register */
158  __O uint32_t IntEnClr; /**< Interrupt Enable Clear Register */
159  __IO uint32_t SoftInt; /**< Software Interrupt Register */
160  __O uint32_t SoftIntClr; /**< Software Interrupt Clear Register */
161  __IO uint32_t Protection; /**< Protection Enable Register */
162 #if i_MCU_MODEL >= 2300
163  __IO uint32_t SWPrioMask;/**< Software Priority Mask Register */
164  uint32_t _pad0[4];
165 #else
166  uint32_t _pad0[3];
167  __IO uint32_t VectAddress; /**< Vector Address Register */
168  __IO uint32_t DefVectAddr; /**< Default Vector Address Register */
169 #endif
170  uint32_t _pad1[50];
171  __IO uint32_t VectAddr[VIC_SIZE]; /**< Vector Address Registers */
172  uint32_t _pad2[64-VIC_SIZE];
173  __IO uint32_t VectCntl[VIC_SIZE]; /**< Vector Control Registers */
174 #if i_MCU_MODEL >= 2300
175  uint32_t _pad3[800];
176  __IO uint32_t VectAddress; /**< Vector Address Register */
177 #else
178 #endif
179 } VIC_TypeDef;
180 
181 
182 
183 #define VIC_MAX_IRQ_NUMBER (VIC_SIZE-1)
184 
185 #if i_MCU_MODEL >= 2300
186  #define VIC_HIGHEST_PRIORITY 0x0
187  #define VIC_HIGH_PRIORITY ((1<<(__NVIC_PRIO_BITS - 2)) - 1)
188  #define VIC_MEDIUM_PRIORITY ((1<<(__NVIC_PRIO_BITS - 1)) - 1)
189  #define VIC_LOW_PRIORITY ((1<<(__NVIC_PRIO_BITS - 2))*3 - 1)
190  #define VIC_LOWEST_PRIORITY ((1<<(__NVIC_PRIO_BITS )) - 1)
191 
192  // Vector Control Register bit definitions
193  /// Vector Control Register -- Vector Interrupt Controller Enable
194  #define VIC_ENABLE (1 << 5)
195 
196  /// Vector Control Register -- Convert Channel Number to Bit Value
197  #define VIC_BIT(chan) (1 << (chan))
198 #endif
199 
200 
201 /*-------------System Control Block(SCB)--------------------------------------*/
202 /** @brief System Control (SC) register structure definition
203 
204  System Control Block(SCB) modules include
205  Memory Accelerator Module,
206  Phase Locked Loop,
207  VPB divider,
208  Power Control,
209  External Interrupt,
210  Reset, and
211  Code Security/Debugging
212  */
213 
214 
215 /** @brief System Control (SC) register structure definition */
216 typedef struct
217 {
218  __IO uint32_t MAMCR;/**< Memory Accelerator Module (MAM) */
219  __IO uint32_t MAMTIM; /*0x4*/
220  uint32_t RESERVED0[14];
221  __IO uint32_t MEMMAP; /*0x40*/
222  uint32_t RESERVED1[15];
223  /* Phase Locked Loop (PLL) */
224  __IO uint32_t PLLCON; /*0x80*/
225  __IO uint32_t PLLCFG;
226  __I uint32_t PLLSTAT;
227  __O uint32_t PLLFEED;
228  uint32_t RESERVED2[12];
229  /* Power Control */
230  __IO uint32_t PCON; /*0xc0*/
231  __IO uint32_t PCONP; /*0xC4*/
232  uint32_t RESERVED3[14];
233  /* Clock Divider */
234  __IO uint32_t APBDIV; /*0x100*/
235  __IO uint32_t CCLKCFG;
236  __IO uint32_t USBCLKCFG;
237  __IO uint32_t CLKSRCSEL;
238  uint32_t RESERVED4[12];
239  /* External Interrupts */
240  __IO uint32_t EXTINT; /*0x140*/
241  __IO uint32_t INTWAKE;
242  __IO uint32_t EXTMODE;
243  __IO uint32_t EXTPOLAR;
244  uint32_t RESERVED5[12];
245  __IO uint32_t RSID; /*0x180*//**< Reset, reset source identification */
246  __IO uint32_t CSPR; /**< RSID, code security protection */
247  __IO uint32_t AHBCFG1; /**< AHB1 configuration */
248  __IO uint32_t AHBCFG2; /**< AHB2 configuration */
249  uint32_t RESERVED6[4]; /*0x190*/
250  /*!!!*/
251  __IO uint32_t SCS; /**< System Controls and Status */ /*c1a0*/
252  uint32_t RESERVED7;
253  __IO uint32_t PCLKSEL0;
254  __IO uint32_t PCLKSEL1;/*0xE01Fc1aC*/
255  uint32_t RESERVED8;
256 /* 0xE01FC1B8 LCD_CFG LCD Configuration and clocking control 0x0 R/W*/
257  __IO uint32_t LCD_CFG;
258  uint32_t RESERVED9;
259  /*USBIntSt USB Interrupt Status R/W 0x8000 0000 0xE01F C1C0*/
260  __IO uint32_t USB_INT_STAT;
261 
262 } LPC_SC_TypeDef;
263 
264 
265 /*--------- PLL -------------------------------------------------------------*/
266 #if (i_MCU_MODEL > 2300)
267 
268  #define LPC_SC_PLLCFG_OSCEN_Pos 5
269  #define LPC_SC_PLLCFG_OSCSTAT_Pos 6
270  #define LPC_SC_PLLCFG_NSEL_Pos 16
271 
272  #define LPC_SC_PLLSTAT_PLLE_Pos 24 /*!< LPC_SC PLLSTAT: PLLE Position */
273 
274  #define PLLCFG_Val (PLL_MValue | (PLL_NValue << 16))
275 #else
276  #define LPC_SC_PLLCFG_NSEL_Pos 5
277  #define LPC_SC_PLLSTAT_PLLE_Pos 8 /*!< LPC_SC PLLSTAT: PLLE Position */
278  #define PLLCFG_Val (PLL_MValue | (PLL_NValue << 5))
279 #endif
280 #define LPC_SC_PLLSTAT_PLLC_Pos (LPC_SC_PLLSTAT_PLLE_Pos + 1)
281 #define LPC_SC_PLLSTAT_PLOCK_Pos (LPC_SC_PLLSTAT_PLLE_Pos + 2)
282 /*MAMCR register */
283 #define LPC_SC_MAM_MODE_DISABLED 0
284 #define LPC_SC_MAM_MODE_PARTIAL 1
285 #define LPC_SC_MAM_MODE_FULL 2
286 
287 
288 /*-------------TIMERS---------------------------------------------------------*/
289 // Timer Interrupt Register Bit Definitions
290 #define TIR_MR0I_Msk (1 << 0) // Interrupt flag for match channel 0
291 #define TIR_MR1I_Msk (1 << 1) // Interrupt flag for match channel 1
292 #define TIR_MR2I_Msk (1 << 2) // Interrupt flag for match channel 2
293 #define TIR_MR3I_Msk (1 << 3) // Interrupt flag for match channel 3
294 #define TIR_CR0I_Msk (1 << 4) // Interrupt flag for capture channel 0 event
295 #define TIR_CR1I_Msk (1 << 5) // Interrupt flag for capture channel 1 event
296 #define TIR_CR2I_Msk (1 << 6) // Interrupt flag for capture channel 2 event
297 #define TIR_CR3I_Msk (1 << 7) // Interrupt flag for capture channel 3 event
298 
299 // PWM Interrupt Register Bit Definitions
300 #define PWMIR_MR0I_Msk (1 << 0) // Interrupt flag for match channel 0
301 #define PWMIR_MR1I_Msk (1 << 1) // Interrupt flag for match channel 1
302 #define PWMIR_MR2I_Msk (1 << 2) // Interrupt flag for match channel 2
303 #define PWMIR_MR3I_Msk (1 << 3) // Interrupt flag for match channel 3
304 #define PWMIR_MR4I_Msk (1 << 8) // Interrupt flag for match channel 4
305 #define PWMIR_MR5I_Msk (1 << 9) // Interrupt flag for match channel 5
306 #define PWMIR_MR6I_Msk (1 << 10) // Interrupt flag for match channel 6
307 #define PWMIR_Msk (0x070F)
308 
309 // Timer Control Register Bit Definitions
310 #define TCR_ENABLE_Msk (1 << 0)
311 #define TCR_RESET_Msk (1 << 1)
312 
313 // Timer Match Control Register Bit Definitions
314 #define TMCR_MR0_I_Msk (1 << 0) // Enable Interrupt when MR0 matches TC
315 #define TMCR_MR0_R_Msk (1 << 1) // Enable Reset of TC upon MR0 match
316 #define TMCR_MR0_S_Msk (1 << 2) // Enable Stop of TC upon MR0 match
317 #define TMCR_MR1_I_Msk (1 << 3) // Enable Interrupt when MR1 matches TC
318 #define TMCR_MR1_R_Msk (1 << 4) // Enable Reset of TC upon MR1 match
319 #define TMCR_MR1_S_Msk (1 << 5) // Enable Stop of TC upon MR1 match
320 #define TMCR_MR2_I_Msk (1 << 6) // Enable Interrupt when MR2 matches TC
321 #define TMCR_MR2_R_Msk (1 << 7) // Enable Reset of TC upon MR2 match
322 #define TMCR_MR2_S_Msk (1 << 8) // Enable Stop of TC upon MR2 match
323 #define TMCR_MR3_I_Msk (1 << 9) // Enable Interrupt when MR3 matches TC
324 #define TMCR_MR3_R_Msk (1 << 10) // Enable Reset of TC upon MR3 match
325 #define TMCR_MR3_S_Msk (1 << 11) // Enable Stop of TC upon MR3 match
326 
327 // Timer Capture Control Register Bit Definitions
328 #define TCCR_CR0_R_Msk (1 << 0) // Enable Rising edge on CAPn.0 will load TC to CR0
329 #define TCCR_CR0_F_Msk (1 << 1) // Enable Falling edge on CAPn.0 will load TC to CR0
330 #define TCCR_CR0_I_Msk (1 << 2) // Enable Interrupt on load of CR0
331 #define TCCR_CR1_R_Msk (1 << 3) // Enable Rising edge on CAPn.1 will load TC to CR1
332 #define TCCR_CR1_F_Msk (1 << 4) // Enable Falling edge on CAPn.1 will load TC to CR1
333 #define TCCR_CR1_I_Msk (1 << 5) // Enable Interrupt on load of CR1
334 #define TCCR_CR2_R_Msk (1 << 6) // Enable Rising edge on CAPn.2 will load TC to CR2
335 #define TCCR_CR2_F_Msk (1 << 7) // Enable Falling edge on CAPn.2 will load TC to CR2
336 #define TCCR_CR2_I_Msk (1 << 8) // Enable Interrupt on load of CR2
337 #define TCCR_CR3_R_Msk (1 << 9) // Enable Rising edge on CAPn.3 will load TC to CR3
338 #define TCCR_CR3_F_Msk (1 << 10) // Enable Falling edge on CAPn.3 will load TC to CR3
339 #define TCCR_CR3_I_Msk (1 << 11) // Enable Interrupt on load of CR3
340 
341 /** @brief Timer (TIM) register structure definition */
342 typedef struct
343 {
344  __IO uint32_t IR; // Interrupt Register
345  __IO uint32_t TCR; // Timer Control Register
346  __IO uint32_t TC; // Timer Counter
347  __IO uint32_t PR; // Prescale Register
348  __IO uint32_t PC; // Prescale Counter Register
349  __IO uint32_t MCR; // Match Control Register
350  __IO uint32_t MR0; // Match Register 0
351  __IO uint32_t MR1; // Match Register 1
352  __IO uint32_t MR2; // Match Register 2
353  __IO uint32_t MR3; // Match Register 3
354  __IO uint32_t CCR; // Capture Control Register
355  __I uint32_t CR0; // Capture Register 0
356  __I uint32_t CR1; // Capture Register 1
357  __I uint32_t CR2; // Capture Register 2
358  __I uint32_t CR3; // Capture Register 3
359  __IO uint32_t EMR; // External Match Register
360  uint32_t RESERVED1[12];
361  __IO uint32_t CTCR;
362 } LPC_TIM_TypeDef;
363 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
364 // PWM Control Register Bit Definitions
365 #define PWMCR_ENABLE_Msk (1 << 0)
366 #define PWMCR_RESET_Msk (1 << 1)
367 /** @brief Pulse-Width Modulation (PWM) register structure definition */
368 typedef struct
369 {
370  __IO uint32_t IR; // Interrupt Register
371  __IO uint32_t TCR; // Timer Control Register
372  __IO uint32_t TC; // Timer Counter
373  __IO uint32_t PR; // Prescale Register
374  __IO uint32_t PC; // Prescale Counter Register
375  __IO uint32_t MCR; // Match Control Register
376  __IO uint32_t MR0; // Match Register 0
377  __IO uint32_t MR1; // Match Register 1
378  __IO uint32_t MR2; // Match Register 2
379  __IO uint32_t MR3; // Match Register 3
380  __IO uint32_t CCR; // Capture Control Register
381  __I uint32_t CR0; // Capture Register 0
382  __I uint32_t CR1; // Capture Register 1
383  __I uint32_t CR2; // Capture Register 2
384  __I uint32_t CR3; // Capture Register 3
385  uint32_t RESERVED0;
386  __IO uint32_t MR4; // Match Register 4
387  __IO uint32_t MR5; // Match Register 5
388  __IO uint32_t MR6; // Match Register 6
389  __IO uint32_t PCR;
390  __IO uint32_t LER;
391  uint32_t RESERVED1[7];
392  __IO uint32_t CTCR;
393 } LPC_PWM_TypeDef;
394 /*-------------PINS-----------------------------------------------------------*/
395 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
396 /** @brief Pin Connect Block (PINCON) register structure definition */
397 typedef struct
398 {
399  __IO uint32_t PINSEL0;
400  __IO uint32_t PINSEL1;
401  __IO uint32_t PINSEL2;
402  __IO uint32_t PINSEL3;
403  __IO uint32_t PINSEL4;
404  __IO uint32_t PINSEL5;
405  __IO uint32_t PINSEL6;
406  __IO uint32_t PINSEL7;
407  __IO uint32_t PINSEL8;
408  __IO uint32_t PINSEL9;
409  __IO uint32_t PINSEL10;
410  uint32_t RESERVED0[5];
411  __IO uint32_t PINMODE0;
412  __IO uint32_t PINMODE1;
413  __IO uint32_t PINMODE2;
414  __IO uint32_t PINMODE3;
415  __IO uint32_t PINMODE4;
416  __IO uint32_t PINMODE5;
417  __IO uint32_t PINMODE6;
418  __IO uint32_t PINMODE7;
419  __IO uint32_t PINMODE8;
420  __IO uint32_t PINMODE9;
421  __IO uint32_t PINMODE10;
422 /* __IO uint32_t PINMODE_OD0;
423  __IO uint32_t PINMODE_OD1;
424  __IO uint32_t PINMODE_OD2;
425  __IO uint32_t PINMODE_OD3;
426  __IO uint32_t PINMODE_OD4;
427  __IO uint32_t I2CPADCFG;
428  */
429 } LPC_PINCON_TypeDef;
430 #if 0
431 #define PINSEL_n(n) (*(REG32*)(LPC_PINSEL_BASE + (n<<2))) /**< get PINSEL REG */
432 
433 #define LPC2XXX_PORT0 0
434 #define LPC2XXX_PORT1 1
435 #define LPC2XXX_PORT2 2
436 #define LPC2XXX_PORT3 3
437 #define LPC2XXX_PORT4 4
438 
439 /**
440  *\if russian_lng
441  * Вычислить общий номер ножки согласно номеру порта и ножки
442  *\else
443  * Calculate common pin number accoding to number of port and pin
444  *\endif
445 \code
446  #define UART_1_TX_PIN_NUMBER PORT_PIN_NUMBER(PORT3,16)
447  #define UART_1_RX_PIN_NUMBER PORT_PIN_NUMBER(PORT3,17)
448 \endcode
449  */
450 #define PORT_PIN_NUMBER(prt,number) (prt*32+number)
451 
452 /**
453  *\if russian_lng
454  * Установать вывод ножки номер number согласно value
455  *
456  * P0[0] имеет номер 0, P1[0] имеет номер 32, P2[2] имеет номер 2*32+2=64 и т.д
457  *\else
458  * Set pin accoding to pin number (number) and its mode (value)
459  *
460  * P0[0] has number0, P1[0] has number 32, P2[2] has number 2*32+2=64 and so on
461  *\endif
462 
463 \code
464  PORT_SELECT_PIN (UART_1_TX_PIN_NUMBER, UART_1_TX_PIN_SELECT);
465  PORT_SELECT_PIN (UART_1_RX_PIN_NUMBER, UART_1_RX_PIN_SELECT);
466 \endcode
467  */
468 #define PORT_SELECT_PIN(number,value) PINSEL_n(number>>4) = \
469  (PINSEL_n(number>>4) & (~(3<<((number&0xf)<<1)))) | ((value&3)<<((number&0xf)<<1))
470 
471 /** By default 0 configures GP IO*/
472 #define PORT_PIN_MODE_GPIO 0
473 
474 #define PINMODE_n(n) (*(REG32*)(LPC_PINSEL_BASE + 0x40 + (n<<2)))
475 #define PINMODE_PULL_UP 0
476 #define PINMODE_DEFAULT PINMODE_PULL_UP
477 #define PINMODE_NO_PULL_ 2
478 #define PINMODE_PULL_DOWN 3
479 
480 #endif /* 0*/
481 
482 /*-------------General Purpose Input/Output (GPIO)----------------------------*/
483 /** @brief General Purpose Input/Output (GPIO) register structure definition old pins style control
484  */
485 typedef struct
486 {
487  __IO uint32_t PIN;
488  __IO uint32_t SET;
489  __IO uint32_t DIR;
490  __O uint32_t CLR;
491 } LPC_IO_TypeDef_old;
492 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
493 /** @brief General Purpose Input/Output (GPIO) register structure definition */
494 typedef struct
495 {
496  union {
497  __IO uint32_t FIODIR;
498  struct {
499  __IO uint16_t FIODIRL;
500  __IO uint16_t FIODIRH;
501  };
502  struct {
503  __IO uint8_t FIODIR0;
504  __IO uint8_t FIODIR1;
505  __IO uint8_t FIODIR2;
506  __IO uint8_t FIODIR3;
507  };
508  };
509  uint32_t RESERVED0[3];
510  union {
511  __IO uint32_t FIOMASK;
512  struct {
513  __IO uint16_t FIOMASKL;
514  __IO uint16_t FIOMASKH;
515  };
516  struct {
517  __IO uint8_t FIOMASK0;
518  __IO uint8_t FIOMASK1;
519  __IO uint8_t FIOMASK2;
520  __IO uint8_t FIOMASK3;
521  };
522  };
523  union {
524  __IO uint32_t FIOPIN;
525  struct {
526  __IO uint16_t FIOPINL;
527  __IO uint16_t FIOPINH;
528  };
529  struct {
530  __IO uint8_t FIOPIN0;
531  __IO uint8_t FIOPIN1;
532  __IO uint8_t FIOPIN2;
533  __IO uint8_t FIOPIN3;
534  };
535  };
536  union {
537  __IO uint32_t FIOSET;
538  struct {
539  __IO uint16_t FIOSETL;
540  __IO uint16_t FIOSETH;
541  };
542  struct {
543  __IO uint8_t FIOSET0;
544  __IO uint8_t FIOSET1;
545  __IO uint8_t FIOSET2;
546  __IO uint8_t FIOSET3;
547  };
548  };
549  union {
550  __O uint32_t FIOCLR;
551  struct {
552  __O uint16_t FIOCLRL;
553  __O uint16_t FIOCLRH;
554  };
555  struct {
556  __O uint8_t FIOCLR0;
557  __O uint8_t FIOCLR1;
558  __O uint8_t FIOCLR2;
559  __O uint8_t FIOCLR3;
560  };
561  };
562 } LPC_GPIO_TypeDef;
563 
564 /** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
565 typedef struct
566 {
567  __I uint32_t IntStatus;
568  __I uint32_t IO0IntStatR;
569  __I uint32_t IO0IntStatF;
570  __O uint32_t IO0IntClr;
571  __IO uint32_t IO0IntEnR;
572  __IO uint32_t IO0IntEnF;
573  uint32_t RESERVED0[3];
574  __I uint32_t IO2IntStatR;
575  __I uint32_t IO2IntStatF;
576  __O uint32_t IO2IntClr;
577  __IO uint32_t IO2IntEnR;
578  __IO uint32_t IO2IntEnF;
579 } LPC_GPIOINT_TypeDef;
580 #if 0
581 /*-------------GPIO Interrupt Registers --------------------------------------*/
582 #define IO0_INT_EN_R (*(REG32*)(GPIO_BASE + 0x90))
583 #define IO0_INT_EN_F (*(REG32*)(GPIO_BASE + 0x94))
584 #define IO0_INT_STAT_R (*(REG32*)(GPIO_BASE + 0x84))
585 #define IO0_INT_STAT_F (*(REG32*)(GPIO_BASE + 0x88))
586 #define IO0_INT_CLR (*(REG32*)(GPIO_BASE + 0x8C))
587 
588 #define IO2_INT_EN_R (*(REG32*)(GPIO_BASE + 0xB0))
589 #define IO2_INT_EN_F (*(REG32*)(GPIO_BASE + 0xB4))
590 #define IO2_INT_STAT_R (*(REG32*)(GPIO_BASE + 0xA4))
591 #define IO2_INT_STAT_F (*(REG32*)(GPIO_BASE + 0xA8))
592 #define IO2_INT_CLR (*(REG32*)(GPIO_BASE + 0xAC))
593 
594 #define IO_INT_STAT (*(REG32*)(GPIO_BASE + 0x80))
595 
596 #define PARTCFG (*(REG32*)(PARTCFG_BASE + 0x00))
597 /*-------------Fast I/O setup ----------------------------------------------*/
598 #define FIOREG_BASE_ADDR_n(n,off) (*(REG32*)(FIO_BASE + (n<<5)+ off))
599 #define FIOREG_BASE_ADDR_n16(n,off) (*(REG16*)(FIO_BASE + (n<<5)+ off))
600 #define FIOREG_BASE_ADDR_n8(n,off) (*(REG8*)(FIO_BASE + (n<<5)+ off))
601 
602 #define FIO0DIR FIOREG_BASE_ADDR_n(0,0)
603 #define FIO0MASK FIOREG_BASE_ADDR_n(0,0x10)
604 #define FIO0PIN FIOREG_BASE_ADDR_n(0,0x14)
605 #define FIO0SET FIOREG_BASE_ADDR_n(0,0x18)
606 #define FIO0CLR FIOREG_BASE_ADDR_n(0,0x1C)
607 
608 /**FIO DIR CONSTANT TO MAKE PORT BE INPUT*/
609 #define PIN_INPUT 0
610 /**FIO DIR CONSTANT TO MAKE PORT BE OUTPUT*/
611 #define PIN_OUTPUT 1
612 /** SET PIN DIRECTION (PIN_OUTPUT or PIN_INPUT )*/
613 #define PORT_DIRECTION_PIN(number,direction) \
614  FIOREG_BASE_ADDR_n(((number)>>5),0x00) = 1 << ((number)&0x1F); \
615  if ((number>>6) == 0){ \
616  SCS = 1;};
617  /* port0 and port1 turning to new scheme*/
618 
619 /** SET PIN TO HIGHT LEVEL (IF DIRECTION IS PIN_OUTPUT )*/
620 #define PORT_SET_PIN(number) \
621  FIOREG_BASE_ADDR_n(((number)>>5),0x18) = 1 << ((number)&0x1F)
622 /** SET PIN TO LOW LEVEL (IF DIRECTION IS PIN_OUTPUT )*/
623 #define PORT_CLEAR_PIN(number) \
624  FIOREG_BASE_ADDR_n(((number)>>5),0x1C) = 1 << ((number)&0x1F)
625 /** GET VALUE OF PIN*/
626 #define PORT_GET_PIN(number) \
627  (FIOREG_BASE_ADDR_n(((number)>>5),0x14) &(1 << ((number)&0x1F)))
628 
629 #define FIO1DIR FIOREG_BASE_ADDR_n(1,0)
630 #define FIO1MASK FIOREG_BASE_ADDR_n(1,0x10)
631 #define FIO1PIN FIOREG_BASE_ADDR_n(1,0x14)
632 #define FIO1SET FIOREG_BASE_ADDR_n(1,0x18)
633 #define FIO1CLR FIOREG_BASE_ADDR_n(1,0x1C)
634 
635 #define FIO2DIR FIOREG_BASE_ADDR_n(2,0)
636 #define FIO2MASK FIOREG_BASE_ADDR_n(2,0x10)
637 #define FIO2PIN FIOREG_BASE_ADDR_n(2,0x14)
638 #define FIO2SET FIOREG_BASE_ADDR_n(2,0x18)
639 #define FIO2CLR FIOREG_BASE_ADDR_n(2,0x1C)
640 
641 #define FIO3DIR FIOREG_BASE_ADDR_n(3,0)
642 #define FIO3MASK FIOREG_BASE_ADDR_n(3,0x10)
643 #define FIO3PIN FIOREG_BASE_ADDR_n(3,0x14)
644 #define FIO3SET FIOREG_BASE_ADDR_n(3,0x18)
645 #define FIO3CLR FIOREG_BASE_ADDR_n(3,0x1C)
646 
647 #define FIO4DIR FIOREG_BASE_ADDR_n(4,0)
648 #define FIO4MASK FIOREG_BASE_ADDR_n(4,0x10)
649 #define FIO4PIN FIOREG_BASE_ADDR_n(4,0x14)
650 #define FIO4SET FIOREG_BASE_ADDR_n(4,0x18)
651 #define FIO4CLR FIOREG_BASE_ADDR_n(4,0x1C)
652 
653 
654 /* FIOs can be accessed throughFIOREG_BASE_ADDR_n8 WORD, HALF-WORD or BYTE. */
655 #define FIO0DIR0 FIOREG_BASE_ADDR_n8(0,0)
656 #define FIO1DIR0 FIOREG_BASE_ADDR_n8(1,0)
657 #define FIO2DIR0 FIOREG_BASE_ADDR_n8(2,0)
658 #define FIO3DIR0 FIOREG_BASE_ADDR_n8(3,0)
659 #define FIO4DIR0 FIOREG_FIOREG_BASE_ADDR_n8BASE_ADDR_n8(4,0)
660 
661 #define FIO0DIR1 FIOREG_BASE_ADDR_n8(0,1)
662 #define FIO1DIR1 FIOREG_BASE_ADDR_n8(1,1)
663 #define FIO2DIR1 FIOREG_BASE_ADDR_n8(2,1)
664 #define FIO3DIR1 FIOREG_BASE_ADDR_n8(3,1)
665 #define FIO4DIR1 FIOREG_BASE_ADDR_n8(4,1)
666 
667 #define FIO0DIR2 FIOREG_BASE_ADDR_n8(0,2)
668 #define FIO1DIR2 FIOREG_BASE_ADDR_n8(1,2)
669 #define FIO2DIR2 FIOREG_BASE_ADDR_n8(2,2)
670 #define FIO3DIR2 FIOREG_BASE_ADDR_n8(3,2)
671 #define FIO4DIR2 FIOREG_BASE_ADDR_n8(4,2)
672 
673 #define FIO0DIR3 FIOREG_BASE_ADDR_n8(0,3)
674 #define FIO1DIR3 FIOREG_BASE_ADDR_n8(1,3)
675 #define FIO2DIR3 FIOREG_BASE_ADDR_n8(2,3)
676 #define FIO3DIR3 FIOREG_BASE_ADDR_n8(3,3)
677 #define FIO4DIR3 FIOREG_BASE_ADDR_n8(4,3)
678 
679 #define FIO0DIRL FIOREG_BASE_ADDR_n16(0,0)
680 #define FIO1DIRL FIOREG_BASE_ADDR_n16(1,0)
681 #define FIO2DIRL FIOREG_BASE_ADDR_n16(2,0)
682 #define FIO3DIRL FIOREG_BASE_ADDR_n16(3,0)
683 #define FIO4DIRL FIOREG_BASE_ADDR_n16(4,0)
684 
685 #define FIO0DIRU FIOREG_BASE_ADDR_n16(0,2)
686 #define FIO1DIRU FIOREG_BASE_ADDR_n16(1,2)
687 #define FIO2DIRU FIOREG_BASE_ADDR_n16(2,2)
688 #define FIO3DIRU FIOREG_BASE_ADDR_n16(3,2)
689 #define FIO4DIRU FIOREG_BASE_ADDR_n16(4,2)
690 /*-----------------*/
691 #define FIOREG_BASE_ADDR_n8_FIOMASK(letter1,letter2) \
692  FIOREG_BASE_ADDR_n8(letter1,0x10+letter2)
693 
694 #define FIO0MASK0 FIOREG_BASE_ADDR_n8_FIOMASK(0,0)
695 #define FIO1MASK0 FIOREG_BASE_ADDR_n8_FIOMASK(1,0)
696 #define FIO2MASK0 FIOREG_BASE_ADDR_n8_FIOMASK(2,0)
697 #define FIO3MASK0 FIOREG_BASE_ADDR_n8_FIOMASK(3,0)
698 #define FIO4MASK0 FIOREG_BASE_ADDR_n8_FIOMASK(4,0)
699 
700 #define FIO0MASK1 FIOREG_BASE_ADDR_n8_FIOMASK(0,1)
701 #define FIO1MASK1 FIOREG_BASE_ADDR_n8_FIOMASK(1,1)
702 #define FIO2MASK1 FIOREG_BASE_ADDR_n8_FIOMASK(2,1)
703 #define FIO3MASK1 FIOREG_BASE_ADDR_n8_FIOMASK(3,1)
704 #define FIO4MASK1 FIOREG_BASE_ADDR_n8_FIOMASK(4,1)
705 
706 #define FIO0MASK2 FIOREG_BASE_ADDR_n8_FIOMASK(0,2)
707 #define FIO1MASK2 FIOREG_BASE_ADDR_n8_FIOMASK(1,2)
708 #define FIO2MASK2 FIOREG_BASE_ADDR_n8_FIOMASK(2,2)
709 #define FIO3MASK2 FIOREG_BASE_ADDR_n8_FIOMASK(3,2)
710 #define FIO4MASK2 FIOREG_BASE_ADDR_n8_FIOMASK(4,2)
711 
712 #define FIO0MASK3 FIOREG_BASE_ADDR_n8_FIOMASK(0,3)
713 #define FIO1MASK3 FIOREG_BASE_ADDR_n8_FIOMASK(1,3)
714 #define FIO2MASK3 FIOREG_BASE_ADDR_n8_FIOMASK(2,3)
715 #define FIO3MASK3 FIOREG_BASE_ADDR_n8_FIOMASK(3,3)
716 #define FIO4MASK3 FIOREG_BASE_ADDR_n8_FIOMASK(4,3)
717 /*-----------------*/
718 #define FIOREG_BASE_ADDR_n16_FIOMASKL(letter1) \
719  FIOREG_BASE_ADDR_n16(letter1,0x10)
720 
721 #define FIOREG_BASE_ADDR_n16_FIOMASKU(letter1) \
722  FIOREG_BASE_ADDR_n16(letter1,0x12)
723 
724 #define FIO0MASKL FIOREG_BASE_ADDR_n16_FIOMASKL(0)
725 #define FIO1MASKL FIOREG_BASE_ADDR_n16_FIOMASKL(1)
726 #define FIO2MASKL FIOREG_BASE_ADDR_n16_FIOMASKL(2)
727 #define FIO3MASKL FIOREG_BASE_ADDR_n16_FIOMASKL(3)
728 #define FIO4MASKL FIOREG_BASE_ADDR_n16_FIOMASKL(4)
729 
730 #define FIO0MASKU FIOREG_BASE_ADDR_n16_FIOMASKU(0)
731 #define FIO1MASKU FIOREG_BASE_ADDR_n16_FIOMASKU(1)
732 #define FIO2MASKU FIOREG_BASE_ADDR_n16_FIOMASKU(2)
733 #define FIO3MASKU FIOREG_BASE_ADDR_n16_FIOMASKU(3)
734 #define FIO4MASKU FIOREG_BASE_ADDR_n16_FIOMASKU(4)
735 /*-----------------*/ /*-----------------*/
736 #define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE + 0x14))
737 #define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE + 0x34))
738 #define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE + 0x54))
739 #define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE + 0x74))
740 #define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE + 0x94))
741 
742 #define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE + 0x15))
743 #define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE + 0x35))
744 #define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE + 0x55))
745 #define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE + 0x75))
746 #define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE + 0x95))
747 
748 #define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE + 0x16))
749 #define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE + 0x36))
750 #define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE + 0x56))
751 #define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE + 0x76))
752 #define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE + 0x96))
753 
754 #define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE + 0x17))
755 #define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE + 0x37))
756 #define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE + 0x57))
757 #define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE + 0x77))
758 #define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE + 0x97))
759 
760 #define FIO0PINL (*(volatile unsigned short *)(FIO_BASE + 0x14))
761 #define FIO1PINL (*(volatile unsigned short *)(FIO_BASE + 0x34))
762 #define FIO2PINL (*(volatile unsigned short *)(FIO_BASE + 0x54))
763 #define FIO3PINL (*(volatile unsigned short *)(FIO_BASE + 0x74))
764 #define FIO4PINL (*(volatile unsigned short *)(FIO_BASE + 0x94))
765 
766 #define FIO0PINU (*(volatile unsigned short *)(FIO_BASE + 0x16))
767 #define FIO1PINU (*(volatile unsigned short *)(FIO_BASE + 0x36))
768 #define FIO2PINU (*(volatile unsigned short *)(FIO_BASE + 0x56))
769 #define FIO3PINU (*(volatile unsigned short *)(FIO_BASE + 0x76))
770 #define FIO4PINU (*(volatile unsigned short *)(FIO_BASE + 0x96))
771 
772 #define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE + 0x18))
773 #define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE + 0x38))
774 #define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE + 0x58))
775 #define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE + 0x78))
776 #define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE + 0x98))
777 
778 #define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE + 0x19))
779 #define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE + 0x29))
780 #define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE + 0x59))
781 #define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE + 0x79))
782 #define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE + 0x99))
783 
784 #define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE + 0x1A))
785 #define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE + 0x3A))
786 #define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE + 0x5A))
787 #define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE + 0x7A))
788 #define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE + 0x9A))
789 
790 #define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE + 0x1B))
791 #define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE + 0x3B))
792 #define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE + 0x5B))
793 #define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE + 0x7B))
794 #define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE + 0x9B))
795 
796 #define FIO0SETL (*(volatile unsigned short *)(FIO_BASE + 0x18))
797 #define FIO1SETL (*(volatile unsigned short *)(FIO_BASE + 0x38))
798 #define FIO2SETL (*(volatile unsigned short *)(FIO_BASE + 0x58))
799 #define FIO3SETL (*(volatile unsigned short *)(FIO_BASE + 0x78))
800 #define FIO4SETL (*(volatile unsigned short *)(FIO_BASE + 0x98))
801 
802 #define FIO0SETU (*(volatile unsigned short *)(FIO_BASE + 0x1A))
803 #define FIO1SETU (*(volatile unsigned short *)(FIO_BASE + 0x3A))
804 #define FIO2SETU (*(volatile unsigned short *)(FIO_BASE + 0x5A))
805 #define FIO3SETU (*(volatile unsigned short *)(FIO_BASE + 0x7A))
806 #define FIO4SETU (*(volatile unsigned short *)(FIO_BASE + 0x9A))
807 
808 #define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE + 0x1C))
809 #define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE + 0x3C))
810 #define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE + 0x5C))
811 #define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE + 0x7C))
812 #define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE + 0x9C))
813 
814 #define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE + 0x1D))
815 #define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE + 0x2D))
816 #define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE + 0x5D))
817 #define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE + 0x7D))
818 #define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE + 0x9D))
819 
820 #define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE + 0x1E))
821 #define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE + 0x3E))
822 #define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE + 0x5E))
823 #define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE + 0x7E))
824 #define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE + 0x9E))
825 
826 #define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE + 0x1F))
827 #define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE + 0x3F))
828 #define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE + 0x5F))
829 #define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE + 0x7F))
830 #define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE + 0x9F))
831 
832 #define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE + 0x1E))
833 #define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE + 0x3E))
834 #define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE + 0x5E))
835 #define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE + 0x7E))
836 #define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE + 0x9E))
837 
838 /* \todo Migrating to the LPC2300/2400 family
839 The following key improvements have been done to the VIC:
840 1. VIC register accesses are now controlled by software using the Protection Enable
841 register (VICProtection-0xFFFF F020). This register is accessible only in an ARM
842 privileged mode.
843 2. The VICAddress register resides in a new location in memory, i.e. 0xFFFF FF00.
844 Hence the IRQ interrupt vector (residing at 0x18) should now be modified as:
845  LDR PC, [PC, # -0x0120]
846  Previously, the instruction would be:
847  LDR PC, [PC, # -0x0FF0]
848 3. Spurious interrupts can no longer occur in the LPC23xx/LPC24xx. Hence the Default
849 Address Register is no longer available in this family.
850  */
851 
852 #endif /*0 */
853 /*------Universal Asynchronous Receiver PINS (UART0)--------------------------*/
854 #ifndef UART_0_TX_PIN_NUMBER
855 #if i_MCU_MODEL >= 2300
856  #define UART_0_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,2)/**< PINSEL0 Mask for UART0 */
857 #else
858  #define UART_0_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,0)/**< PINSEL0 Mask for UART0 */
859 
860 #endif
861 #endif
862 #ifndef UART_0_RX_PIN_NUMBER
863 #define UART_0_RX_PIN_NUMBER (UART_0_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART0*/
864 #endif
865 #ifndef UART_0_TX_PIN_SELECT
866 #define UART_0_TX_PIN_SELECT 1 /**<PINSEL0 Value for UART0*/
867 #endif
868 #ifndef UART_0_RX_PIN_SELECT
869 #define UART_0_RX_PIN_SELECT UART_0_TX_PIN_SELECT /**<PINSEL0 Value for UART0*/
870 #endif
871 
872 #ifndef UART_1_TX_PIN_NUMBER
873 #if i_MCU_MODEL >= 2300
874  #define UART_1_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,10)/**< PINSEL0 Mask for UART1*/
875 #else
876  #define UART_1_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,8)/**< PINSEL0 Mask for UART1*/
877 
878 #endif
879 #endif
880 
881 #ifndef UART_1_RX_PIN_NUMBER
882 #define UART_1_RX_PIN_NUMBER (UART_1_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART1*/
883 #endif
884 #ifndef UART_1_TX_PIN_SELECT
885 #define UART_1_TX_PIN_SELECT 1 /**<PINSEL0 Value for UART1*/
886 #endif
887 #ifndef UART_1_RX_PIN_SELECT
888 #define UART_1_RX_PIN_SELECT UART_1_TX_PIN_SELECT /**<PINSEL0 Value for UART1*/
889 #endif
890 #if i_MCU_MODEL >= 2300
891 #ifndef UART_2_TX_PIN_NUMBER
892  #define UART_2_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,10)/**< PINSEL0 Mask*/
893 #endif
894 #ifndef UART_2_RX_PIN_NUMBER
895  #define UART_2_RX_PIN_NUMBER (UART_2_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART0*/
896 #endif
897 #ifndef UART_2_TX_PIN_SELECT
898  #define UART_2_TX_PIN_SELECT 1 /**<PINSEL Value for UART1*/
899 #endif
900 #ifndef UART_2_RX_PIN_SELECT
901  #define UART_2_RX_PIN_SELECT UART_2_TX_PIN_SELECT /**<PINSEL0 Value for UART1*/
902 #endif
903 
904 
905 
906 
907 #ifndef UART_3_TX_PIN_NUMBER
908  #define UART_3_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,25)/**< PINSEL0 Mask*/
909 #endif
910 #ifndef UART_3_RX_PIN_NUMBER
911  #define UART_3_RX_PIN_NUMBER (UART_3_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART0*/
912 #endif
913 #ifndef UART_3_TX_PIN_SELECT
914  #define UART_3_TX_PIN_SELECT 3 /**<PINSEL Value for UART1*/
915 #endif
916 #ifndef UART_3_RX_PIN_SELECT
917  #define UART_3_RX_PIN_SELECT UART_3_TX_PIN_SELECT /**<PINSEL0 Value for UART1*/
918 #endif
919 #endif
920 
921 
922 /*------Universal Asynchronous Receiver Transmitter 0 (UART0)-----------------*/
923 /** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */
924 typedef struct
925 {
926  union {
927  __I uint8_t RBR;
928  __O uint8_t THR;
929  __IO uint8_t DLL;
930  uint32_t RESERVED0;
931  };
932  union {
933  __IO uint8_t DLM;
934  __IO uint32_t IER;
935  };
936  union {
937  __I uint32_t IIR;
938  __O uint8_t FCR;
939  };
940  __IO uint8_t LCR;
941  uint8_t RESERVED1[7];
942  __I uint8_t LSR;
943  uint8_t RESERVED2[7];
944  __IO uint8_t SCR;
945  uint8_t RESERVED3[3];
946  __IO uint32_t ACR;
947  __IO uint8_t ICR;
948  uint8_t RESERVED4[3];
949  __IO uint8_t FDR;
950  uint8_t RESERVED5[7];
951  __IO uint8_t TER;
952 /*
953  uint8_t RESERVED6[39];
954  __I uint8_t FIFOLVL;*/
955 } LPC_UART_TypeDef;
956 
957 /** @brief Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */
958 typedef struct
959 {
960  union {
961  __I uint8_t RBR;
962  __O uint8_t THR;
963  __IO uint8_t DLL;
964  uint32_t RESERVED0;
965  };
966  union {
967  __IO uint8_t DLM;
968  __IO uint32_t IER;
969  };
970  union {
971  __I uint32_t IIR;
972  __O uint8_t FCR;
973  };
974  __IO uint8_t LCR;
975  uint8_t RESERVED1[3];
976  __IO uint8_t MCR;
977  uint8_t RESERVED2[3];
978  __I uint8_t LSR;
979  uint8_t RESERVED3[3];
980  __I uint8_t MSR;
981  uint8_t RESERVED4[3];
982  __IO uint8_t SCR;
983  uint8_t RESERVED5[3];
984  __IO uint32_t ACR;
985  uint32_t RESERVED6;
986  __IO uint32_t FDR;
987  uint32_t RESERVED7;
988  __IO uint8_t TER;
989 /* uint8_t RESERVED6[39];
990  __I uint8_t FIFOLVL;*/
991 } LPC_UART1_TypeDef;
992 
993 
994 /*------I2C Interface 0 (I2C0)------------------------------------------------*/
995 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
996 /** @brief Inter-Integrated Circuit (I2C) register structure definition */
997 typedef struct
998 {
999  __IO uint32_t I2CONSET;
1000  __I uint32_t I2STAT;
1001  __IO uint32_t I2DAT;
1002  __IO uint32_t I2ADR0;
1003  __IO uint32_t I2SCLH;
1004  __IO uint32_t I2SCLL;
1005  __O uint32_t I2CONCLR;
1006  /* __IO uint32_t MMCTRL;
1007  __IO uint32_t I2ADR1;
1008  __IO uint32_t I2ADR2;
1009  __IO uint32_t I2ADR3;
1010  __I uint32_t I2DATA_BUFFER;
1011  __IO uint32_t I2MASK0;
1012  __IO uint32_t I2MASK1;
1013  __IO uint32_t I2MASK2;
1014  __IO uint32_t I2MASK3;
1015  */
1016 } LPC_I2C_TypeDef;
1017 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
1018 /** @brief Inter IC Sound (I2S) register structure definition */
1019 typedef struct
1020 {
1021  __IO uint32_t I2SDAO;
1022  __IO uint32_t I2SDAI;
1023  __O uint32_t I2STXFIFO;
1024  __I uint32_t I2SRXFIFO;
1025  __I uint32_t I2SSTATE;
1026  __IO uint32_t I2SDMA1;
1027  __IO uint32_t I2SDMA2;
1028  __IO uint32_t I2SIRQ;
1029  __IO uint32_t I2STXRATE;
1030  __IO uint32_t I2SRXRATE;
1031  /*
1032  __IO uint32_t I2STXBITRATE;
1033  __IO uint32_t I2SRXBITRATE;
1034  __IO uint32_t I2STXMODE;
1035  __IO uint32_t I2SRXMODE;*/
1036 } LPC_I2S_TypeDef;
1037 
1038 /*------SPI0 (Serial Peripheral Interface 0) ---------------------------------*/
1039 #if i_MCU_MODEL >= 2300
1040 #ifndef SPI_0_SCK_PIN_NUMBER
1041  #define SPI_0_SCK_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,15)/**< PINSEL0 Mask for SPI */
1042 #endif
1043 #ifndef SPI_0_SEL_PIN_NUMBER
1044  #define SPI_0_SEL_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 1)
1045 #endif
1046 #ifndef SPI_0_MISO_PIN_NUMBER
1047  #define SPI_0_MISO_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 2)
1048 #endif
1049 #ifndef SPI_0_ALL_PIN_SELECT
1050  #define SPI_0_ALL_PIN_SELECT 3
1051 #endif
1052 #ifndef SSP_0_ALL_PIN_SELECT
1053  #define SSP_0_ALL_PIN_SELECT 2
1054 #endif
1055 #else /* i_MCU_MODEL >= 2300*/
1056 #ifndef SPI_0_ALL_PIN_SELECT
1057  #define SPI_0_ALL_PIN_SELECT 2
1058 #endif
1059 
1060 #ifndef SPI_0_SCK_PIN_NUMBER
1061  #define SPI_0_SCK_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,4)
1062 #endif
1063 #ifndef SPI_0_MISO_PIN_NUMBER
1064  #define SPI_0_MISO_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 1)
1065 #endif
1066 #ifndef SPI_0_SEL_PIN_NUMBER
1067  #define SPI_0_SEL_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 3)
1068 #endif
1069 
1070 
1071 #endif
1072 #ifndef SPI_0_MOSI_PIN_NUMBER
1073  #define SPI_0_MOSI_PIN_NUMBER (SPI_0_MISO_PIN_NUMBER + 1) /* always after MISO*/
1074 #endif
1075 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
1076 /** @brief Serial Peripheral Interface (SPI) register structure definition */
1077 typedef struct
1078 {
1079  __IO uint32_t SPCR;
1080  __I uint32_t SPSR;
1081  __IO uint32_t SPDR;
1082  __IO uint32_t SPCCR;
1083  __I uint32_t SPTCR;/*?? copy of control ??Test Control Register*/
1084  __I uint32_t SPTSR; /*?? copy of status ??Test Status Register*/
1085  uint32_t RESERVED0;
1086  __IO uint32_t SPINT;
1087 } LPC_SPI_TypeDef;
1088 
1089 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
1090 /** @brief Synchronous Serial Communication (SSP) register structure definition */
1091 typedef struct
1092 {
1093  __IO uint32_t CR0;
1094  __IO uint32_t CR1;
1095  __IO uint32_t DR;
1096  __I uint32_t SR;
1097  __IO uint32_t CPSR;
1098  __IO uint32_t IMSC;
1099  __IO uint32_t RIS;
1100  __IO uint32_t MIS;
1101  __IO uint32_t ICR;
1102  __IO uint32_t DMACR;
1103 } LPC_SSP_TypeDef;
1104 
1105 
1106 /*-------------- Real Time Clock --------------------------------------------*/
1107 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
1108 /** @brief Real-Time Clock (RTC) register structure definition */
1109 typedef struct
1110 {
1111  __IO uint8_t ILR;
1112  uint8_t RESERVED0[7];
1113  __IO uint8_t CCR;
1114  uint8_t RESERVED1[3];
1115  __IO uint8_t CIIR;
1116  uint8_t RESERVED2[3];
1117  __IO uint8_t AMR;
1118  uint8_t RESERVED3[3];
1119  __I uint32_t CTIME0;
1120  __I uint32_t CTIME1;
1121  __I uint32_t CTIME2;
1122  __IO uint8_t SEC;
1123  uint8_t RESERVED4[3];
1124  __IO uint8_t MIN;
1125  uint8_t RESERVED5[3];
1126  __IO uint8_t HOUR;
1127  uint8_t RESERVED6[3];
1128  __IO uint8_t DOM;
1129  uint8_t RESERVED7[3];
1130  __IO uint8_t DOW;
1131  uint8_t RESERVED8[3];
1132  __IO uint16_t DOY;
1133  uint16_t RESERVED9;
1134  __IO uint8_t MONTH;
1135  uint8_t RESERVED10[3];
1136  __IO uint16_t YEAR;
1137  uint16_t RESERVED11;
1138 /*
1139  __IO uint32_t CALIBRATION;
1140  __IO uint32_t GPREG0;
1141  __IO uint32_t GPREG1;
1142  __IO uint32_t GPREG2;
1143  __IO uint32_t GPREG3;
1144  __IO uint32_t GPREG4;
1145  __IO uint8_t RTC_AUXEN;
1146  uint8_t RESERVED12[3];
1147  __IO uint8_t RTC_AUX;
1148  uint8_t RESERVED13[3];
1149  */
1150  uint32_t RESERVED13[8];
1151  __IO uint8_t ALSEC;
1152  uint8_t RESERVED14[3];
1153  __IO uint8_t ALMIN;
1154  uint8_t RESERVED15[3];
1155  __IO uint8_t ALHOUR;
1156  uint8_t RESERVED16[3];
1157  __IO uint8_t ALDOM;
1158  uint8_t RESERVED17[3];
1159  __IO uint8_t ALDOW;
1160  uint8_t RESERVED18[3];
1161  __IO uint16_t ALDOY;
1162  uint16_t RESERVED19;
1163  __IO uint8_t ALMON;
1164  uint8_t RESERVED20[3];
1165  __IO uint16_t ALYEAR;
1166  uint16_t RESERVED21;
1167 } LPC_RTC_TypeDef;
1168 
1169 
1170 /*------------------------ A/D Converter 0 (AD0) -----------------------------*/
1171 /** @brief Analog-to-Digital Converter (ADC) register structure definition */
1172 typedef struct
1173 {
1174  __IO uint32_t ADCR;
1175  __IO uint32_t ADGDR;
1176  uint32_t RESERVED0;
1177  __IO uint32_t ADINTEN;
1178  __I uint32_t ADDR0;
1179  __I uint32_t ADDR1;
1180  __I uint32_t ADDR2;
1181  __I uint32_t ADDR3;
1182  __I uint32_t ADDR4;
1183  __I uint32_t ADDR5;
1184  __I uint32_t ADDR6;
1185  __I uint32_t ADDR7;
1186  __I uint32_t ADSTAT;
1187 } LPC_ADC_TypeDef;
1188 
1189 
1190 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
1191 /** @brief Digital-to-Analog Converter (DAC) register structure definition */
1192 typedef struct
1193 {
1194  __IO uint32_t DACR;
1195 /* __IO uint32_t DACCTRL;
1196  __IO uint16_t DACCNTVAL;*/
1197 } LPC_DAC_TypeDef;
1198 /*-------------------------------- Watchdog-----------------------------*/
1199 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
1200 /** @brief Watchdog Timer (WDT) register structure definition */
1201 typedef struct
1202 {
1203  __IO uint8_t WDMOD;
1204  uint8_t RESERVED0[3];
1205  __IO uint32_t WDTC;
1206  __O uint8_t WDFEED;
1207  uint8_t RESERVED1[3];
1208  __I uint32_t WDTV;
1209  __IO uint32_t WDCLKSEL;
1210 } LPC_WDT_TypeDef;
1211 /*------------- Controller Area Network (CAN) --------------------------------*/
1212 /** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
1213 typedef struct
1214 {
1215  __IO uint32_t mask[512]; /* ID Masks */
1216 } LPC_CANAF_RAM_TypeDef;
1217 
1218 /** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
1219 typedef struct /* Acceptance Filter Registers */
1220 {
1221  __IO uint32_t AFMR;
1222  __IO uint32_t SFF_sa;
1223  __IO uint32_t SFF_GRP_sa;
1224  __IO uint32_t EFF_sa;
1225  __IO uint32_t EFF_GRP_sa;
1226  __IO uint32_t ENDofTable;
1227  __I uint32_t LUTerrAd;
1228  __I uint32_t LUTerr;
1229  __IO uint32_t FCANIE;
1230  __IO uint32_t FCANIC0;
1231  __IO uint32_t FCANIC1;
1232 } LPC_CANAF_TypeDef;
1233 
1234 /** @brief Controller Area Network Central (CANCR) register structure definition */
1235 typedef struct /* Central Registers */
1236 {
1237  __I uint32_t CANTxSR;
1238  __I uint32_t CANRxSR;
1239  __I uint32_t CANMSR;
1240 } LPC_CANCR_TypeDef;
1241 
1242 /** @brief Controller Area Network Controller (CAN) register structure definition */
1243 typedef struct /* Controller Registers */
1244 {
1245  __IO uint32_t MOD;
1246  __O uint32_t CMR;
1247  __IO uint32_t GSR;
1248  __I uint32_t ICR;
1249  __IO uint32_t IER;
1250  __IO uint32_t BTR;
1251  __IO uint32_t EWL;
1252  __I uint32_t SR;
1253  __IO uint32_t RFS;
1254  __IO uint32_t RID;
1255  __IO uint32_t RDA;
1256  __IO uint32_t RDB;
1257  __IO uint32_t TFI1;
1258  __IO uint32_t TID1;
1259  __IO uint32_t TDA1;
1260  __IO uint32_t TDB1;
1261  __IO uint32_t TFI2;
1262  __IO uint32_t TID2;
1263  __IO uint32_t TDA2;
1264  __IO uint32_t TDB2;
1265  __IO uint32_t TFI3;
1266  __IO uint32_t TID3;
1267  __IO uint32_t TDA3;
1268  __IO uint32_t TDB3;
1269 } LPC_CAN_TypeDef;
1270 
1271 
1272 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
1273 #if (i_MCU_MODEL >= 2300)
1274 /** @brief Ethernet Media Access Controller (EMAC) register structure definition */
1275 typedef struct
1276 {
1277  __IO uint32_t MAC1; /* MAC config reg 1 */
1278  __IO uint32_t MAC2; /* MAC config reg 2 */
1279  __IO uint32_t IPGT; /* b2b InterPacketGap reg */
1280  __IO uint32_t IPGR; /* non b2b InterPacketGap reg */
1281  __IO uint32_t CLRT; /* CoLlision window/ReTry reg */
1282  __IO uint32_t MAXF; /* MAXimum Frame reg */
1283  __IO uint32_t SUPP; /* PHY SUPPort reg */
1284  __IO uint32_t TEST; /* TEST reg */
1285  __IO uint32_t MCFG; /* MII Mgmt ConFiG reg */
1286  __IO uint32_t MCMD; /* MII Mgmt CoMmanD reg */
1287  __IO uint32_t MADR; /* MII Mgmt ADdRess reg */
1288  __O uint32_t MWTD; /* MII Mgmt WriTe Data reg (WO) */
1289  __I uint32_t MRDD; /* MII Mgmt ReaD Data reg (RO) */
1290  __I uint32_t MIND; /* MII Mgmt INDicators reg (RO) */
1291  uint32_t RESERVED0[2];
1292  __IO uint32_t SA0; /* Station Address 0 reg */
1293  __IO uint32_t SA1; /* Station Address 1 reg */
1294  __IO uint32_t SA2; /* Station Address 2 reg */
1295  uint32_t RESERVED1[45]; /*-------------- Control Registers */
1296  __IO uint32_t Command; /* Command reg */
1297  __I uint32_t Status; /* Status reg (RO) */
1298  __IO uint32_t RxDescriptor; /* Rx descriptor base address reg */
1299  __IO uint32_t RxStatus; /* Rx status base address reg */
1300  __IO uint32_t RxDescriptorNumber; /* Rx number of descriptors reg */
1301  __I uint32_t RxProduceIndex; /* Rx produce index reg (RO) */
1302  __IO uint32_t RxConsumeIndex; /* Rx consume index reg */
1303  __IO uint32_t TxDescriptor; /* Tx descriptor base address reg */
1304  __IO uint32_t TxStatus; /* Tx status base address reg */
1305  __IO uint32_t TxDescriptorNumber; /* Tx number of descriptors reg */
1306  __IO uint32_t TxProduceIndex; /* Tx produce index reg */
1307  __I uint32_t TxConsumeIndex; /* Tx consume index reg (RO) */
1308  uint32_t RESERVED2[10];
1309  __I uint32_t TSV0; /* Tx status vector 0 reg (RO) */
1310  __I uint32_t TSV1; /* Tx status vector 1 reg (RO) */
1311  __I uint32_t RSV; /* Rx status vector reg (RO) */
1312  uint32_t RESERVED3[3];
1313  __IO uint32_t FlowControlCounter; /* Flow control counter reg */
1314  __I uint32_t FlowControlStatus; /* Flow control status reg */
1315  uint32_t RESERVED4[34];
1316  __IO uint32_t RxFilterCtrl; /* Rx filter ctrl reg */
1317  __I uint32_t RxFilterWoLStatus; /* Rx filter WoL status reg (RO) */
1318  __O uint32_t RxFilterWoLClear; /* Rx filter WoL clear reg (WO) */
1319  uint32_t RESERVED5;
1320  __IO uint32_t HashFilterL; /* Hash filter LSBs reg */
1321  __IO uint32_t HashFilterH; /* Hash filter MSBs reg */
1322 
1323  uint32_t RESERVED6[882];/* ----------Module Control Registers----- */
1324  __I uint32_t IntStatus; /* Interrupt status reg (RO) */
1325  __IO uint32_t IntEnable; /* Interrupt enable reg */
1326  __O uint32_t IntClear; /* Interrupt clear reg (WO) */
1327  __O uint32_t IntSet; /* Interrupt set reg (WO) */
1328  uint32_t RESERVED7;
1329  __IO uint32_t PowerDown; /* Power-down reg */
1330  uint32_t RESERVED8;
1331  __I uint32_t Module_ID; /* Module ID reg (RO) */
1332 } LPC_EMAC_TypeDef;
1333 #endif
1334 /*------------- LCD controller (LCD) -----------------------------------------*/
1335 #if (i_MCU_MODEL >= 2470)
1336 /** @brief LCD controller (LCD) register structure definition */
1337 typedef struct
1338 {
1339  __IO uint32_t TIMH; /* LCD Registers */
1340  __IO uint32_t TIMV;
1341  __IO uint32_t POL;
1342  __IO uint32_t LE;
1343  __IO uint32_t UPBASE;
1344  __IO uint32_t LPBASE;
1345  __IO uint32_t CTRL;
1346  __IO uint32_t INTMSK;
1347  __I uint32_t INTRAW;
1348  __I uint32_t INTSTAT;
1349  __O uint32_t INTCLR;
1350  __I uint32_t UPCURR;
1351  __I uint32_t LPCURR;
1352  uint32_t RESERVED0[115];
1353  __IO uint32_t PAL[128];
1354  uint32_t RESERVED1[256];
1355  __IO uint32_t CRSR_IMG[256];
1356  __IO uint32_t CRSR_CTRL;
1357  __IO uint32_t CRSR_CFG;
1358  __IO uint32_t CRSR_PAL0;
1359  __IO uint32_t CRSR_PAL1;
1360  __IO uint32_t CRSR_XY;
1361  __IO uint32_t CRSR_CLIP;
1362  uint32_t RESERVED2[2];
1363  __IO uint32_t CRSR_INTMSK;
1364  __O uint32_t CRSR_INTCLR;
1365  __I uint32_t CRSR_INTRAW;
1366  __I uint32_t CRSR_INTSTAT;
1367 } LPC_LCD_TypeDef;
1368 #endif
1369 /*------------- External Memory Controller (EMC) -----------------------------*/
1370 #if (i_MCU_MODEL >= 2420)
1371 /** @brief External Memory Controller (EMC) register structure definition */
1372 typedef struct
1373 {
1374  __IO uint32_t Control;
1375  __I uint32_t Status;
1376  __IO uint32_t Config;
1377  uint32_t RESERVED0[5];
1378  __IO uint32_t DynamicControl;
1379  __IO uint32_t DynamicRefresh;
1380  __IO uint32_t DynamicReadConfig;
1381  uint32_t RESERVED1[1];
1382  __IO uint32_t DynamicRP;
1383  __IO uint32_t DynamicRAS;
1384  __IO uint32_t DynamicSREX;
1385  __IO uint32_t DynamicAPR;
1386  __IO uint32_t DynamicDAL;
1387  __IO uint32_t DynamicWR;
1388  __IO uint32_t DynamicRC;
1389  __IO uint32_t DynamicRFC;
1390  __IO uint32_t DynamicXSR;
1391  __IO uint32_t DynamicRRD;
1392  __IO uint32_t DynamicMRD;
1393  uint32_t RESERVED2[9];
1394  __IO uint32_t StaticExtendedWait;
1395  uint32_t RESERVED3[31];
1396  __IO uint32_t DynamicConfig0;
1397  __IO uint32_t DynamicRasCas0;
1398  uint32_t RESERVED4[6];
1399  __IO uint32_t DynamicConfig1;
1400  __IO uint32_t DynamicRasCas1;
1401  uint32_t RESERVED5[6];
1402  __IO uint32_t DynamicConfig2;
1403  __IO uint32_t DynamicRasCas2;
1404  uint32_t RESERVED6[6];
1405  __IO uint32_t DynamicConfig3;
1406  __IO uint32_t DynamicRasCas3;
1407  uint32_t RESERVED7[38];
1408  __IO uint32_t StaticConfig0;
1409  __IO uint32_t StaticWaitWen0;
1410  __IO uint32_t StaticWaitOen0;
1411  __IO uint32_t StaticWaitRd0;
1412  __IO uint32_t StaticWaitPage0;
1413  __IO uint32_t StaticWaitWr0;
1414  __IO uint32_t StaticWaitTurn0;
1415  uint32_t RESERVED8[1];
1416  __IO uint32_t StaticConfig1;
1417  __IO uint32_t StaticWaitWen1;
1418  __IO uint32_t StaticWaitOen1;
1419  __IO uint32_t StaticWaitRd1;
1420  __IO uint32_t StaticWaitPage1;
1421  __IO uint32_t StaticWaitWr1;
1422  __IO uint32_t StaticWaitTurn1;
1423  uint32_t RESERVED9[1];
1424  __IO uint32_t StaticConfig2;
1425  __IO uint32_t StaticWaitWen2;
1426  __IO uint32_t StaticWaitOen2;
1427  __IO uint32_t StaticWaitRd2;
1428  __IO uint32_t StaticWaitPage2;
1429  __IO uint32_t StaticWaitWr2;
1430  __IO uint32_t StaticWaitTurn2;
1431  uint32_t RESERVED10[1];
1432  __IO uint32_t StaticConfig3;
1433  __IO uint32_t StaticWaitWen3;
1434  __IO uint32_t StaticWaitOen3;
1435  __IO uint32_t StaticWaitRd3;
1436  __IO uint32_t StaticWaitPage3;
1437  __IO uint32_t StaticWaitWr3;
1438  __IO uint32_t StaticWaitTurn3;
1439 } LPC_EMC_TypeDef;
1440 #endif
1441 /*-------------- MultiMedia Card Interface(MCI) Controller ------------------*/
1442 /** @brief MultiMedia Card Interface(MCI) Controller register structure definition */
1443 typedef struct /* Common Registers */
1444 {
1445  __IO uint8_t POWER;
1446  uint8_t RESERVED0[3];
1447  __IO uint16_t CLOCK ;
1448  uint16_t RESERVED1;
1449  __IO uint32_t ARGUMENT;
1450  __IO uint16_t COMMAND;
1451  uint16_t RESERVED2;
1452  __I uint8_t RESP_CMD ;
1453  uint8_t RESERVED3[3];
1454  __I uint32_t RESP0 ;
1455  __I uint32_t RESP1;
1456  __I uint32_t RESP2;
1457  __I uint32_t RESP3;
1458  __IO uint32_t DATA_TMR ;
1459  __IO uint16_t DATA_LEN ;
1460  uint16_t RESERVED4;
1461  __IO uint8_t DATA_CTRL ;
1462  uint8_t RESERVED5[3];
1463 
1464  __I uint16_t DATA_CNT ;
1465  uint16_t RESERVED6;
1466  __I uint32_t STATUS ;
1467  __O uint16_t CLEAR ;
1468  uint16_t RESERVED7;
1469  __IO uint32_t MASK0 ;
1470  __IO uint32_t MASK1 ;
1471  __IO uint32_t MASK2 ;
1472  __I uint16_t FIFO_CNT ;
1473  uint16_t RESERVED8[3];
1474 
1475  uint32_t RESERVED9[12];
1476  uint32_t FIFO[16];
1477 } LPC_MCI_TypeDef;
1478 
1479 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
1480 /** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
1481 typedef struct /* Common Registers */
1482 {
1483  __I uint32_t DMACIntStat; /*GPDMA_INT_STAT*/
1484  __I uint32_t DMACIntTCStat; /*GPDMA_INT_TCSTAT*/
1485  __O uint32_t DMACIntTCClear; /*GPDMA_INT_TCCLR*/
1486  __I uint32_t DMACIntErrStat; /*GPDMA_INT_ERR_STAT*/
1487  __O uint32_t DMACIntErrClr; /*GPDMA_INT_ERR_CLR*/
1488  __I uint32_t DMACRawIntTCStat; /*GPDMA_RAW_INT_TCSTAT*/
1489  __I uint32_t DMACRawIntErrStat; /*GPDMA_RAW_INT_ERR_STAT*/
1490  __I uint32_t DMACEnbldChns; /*GPDMA_ENABLED_CHNS*/
1491  __IO uint32_t DMACSoftBReq; /*GPDMA_SOFT_BREQ*/
1492  __IO uint32_t DMACSoftSReq; /*GPDMA_SOFT_SREQ*/
1493  __IO uint32_t DMACSoftLBReq; /*GPDMA_SOFT_LBREQ*/
1494  __IO uint32_t DMACSoftLSReq; /*GPDMA_SOFT_LSREQ*/
1495  __IO uint32_t DMACConfig; /*GPDMA_CONFIG*/
1496  __IO uint32_t DMACSync; /*GPDMA_SYNC*/
1497 } LPC_GPDMA_TypeDef;
1498 /*-------------- DMA channel 0,1 registers ----------------------------------*/
1499 /** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
1500 typedef struct /* Channel Registers */
1501 {
1502  __IO uint32_t DMACCSrcAddr; /*GPDMA_CH1_SRC*/
1503  __IO uint32_t DMACCDestAddr; /*GPDMA_CH1_DEST*/
1504  __IO uint32_t DMACCLLI; /*GPDMA_CH1_LLI*/
1505  __IO uint32_t DMACCControl; /*GPDMA_CH1_CTRL*/
1506  __IO uint32_t DMACCConfig; /*GPDMA_CH1_CFG*/
1507 } LPC_GPDMACH_TypeDef;
1508 
1509 /*----------------------------------------------------------------------------*/
1510 /*----------------------------------------------------------------------------*/
1511 /*--------------- USB -------------------------------------------------------*/
1512 /*----------------------------------------------------------------------------*/
1513 /*---------------- USB Controller --------------------------------------------*/
1514 /*------------- Universal Serial Bus (USB) -----------------------------------*/
1515 /** @brief Universal Serial Bus (USB) register structure definition */
1516 typedef struct
1517 {
1518 /* USB Host and OTG registers are for LPC24xx only */
1519 /*------------------------ USB Host Controller -------------------------------*/
1520 /*#define HC_REVISION (*(REG32*)(USBHC_BASE + 0x00))
1521 #define HC_CONTROL (*(REG32*)(USBHC_BASE + 0x04))
1522 #define HC_CMD_STAT (*(REG32*)(USBHC_BASE + 0x08))
1523 #define HC_INT_STAT (*(REG32*)(USBHC_BASE + 0x0C))
1524 #define HC_INT_EN (*(REG32*)(USBHC_BASE + 0x10))
1525 #define HC_INT_DIS (*(REG32*)(USBHC_BASE + 0x14))
1526 #define HC_HCCA (*(REG32*)(USBHC_BASE + 0x18))
1527 #define HC_PERIOD_CUR_ED (*(REG32*)(USBHC_BASE + 0x1C))
1528 #define HC_CTRL_HEAD_ED (*(REG32*)(USBHC_BASE + 0x20))
1529 #define HC_CTRL_CUR_ED (*(REG32*)(USBHC_BASE + 0x24))
1530 #define HC_BULK_HEAD_ED (*(REG32*)(USBHC_BASE + 0x28))
1531 #define HC_BULK_CUR_ED (*(REG32*)(USBHC_BASE + 0x2C))
1532 #define HC_DONE_HEAD (*(REG32*)(USBHC_BASE + 0x30))
1533 #define HC_FM_INTERVAL (*(REG32*)(USBHC_BASE + 0x34))
1534 #define HC_FM_REMAINING (*(REG32*)(USBHC_BASE + 0x38))
1535 #define HC_FM_NUMBER (*(REG32*)(USBHC_BASE + 0x3C))
1536 #define HC_PERIOD_START (*(REG32*)(USBHC_BASE + 0x40))
1537 #define HC_LS_THRHLD (*(REG32*)(USBHC_BASE + 0x44))
1538 #define HC_RH_DESCA (*(REG32*)(USBHC_BASE + 0x48))
1539 #define HC_RH_DESCB (*(REG32*)(USBHC_BASE + 0x4C))
1540 #define HC_RH_STAT (*(REG32*)(USBHC_BASE + 0x50))
1541 #define HC_RH_PORT_STAT1 (*(REG32*)(USBHC_BASE + 0x54))
1542 #define HC_RH_PORT_STAT2 (*(REG32*)(USBHC_BASE + 0x58))
1543 */
1544  __I uint32_t HcRevision; /* USB Host Registers */
1545  __IO uint32_t HcControl;
1546  __IO uint32_t HcCommandStatus;
1547  __IO uint32_t HcInterruptStatus;
1548  __IO uint32_t HcInterruptEnable;
1549  __IO uint32_t HcInterruptDisable;
1550  __IO uint32_t HcHCCA;
1551  __I uint32_t HcPeriodCurrentED;
1552  __IO uint32_t HcControlHeadED;
1553  __IO uint32_t HcControlCurrentED;
1554  __IO uint32_t HcBulkHeadED;
1555  __IO uint32_t HcBulkCurrentED;
1556  __I uint32_t HcDoneHead;
1557  __IO uint32_t HcFmInterval;
1558  __I uint32_t HcFmRemaining;
1559  __I uint32_t HcFmNumber;
1560  __IO uint32_t HcPeriodicStart;
1561  __IO uint32_t HcLSTreshold;
1562  __IO uint32_t HcRhDescriptorA;
1563  __IO uint32_t HcRhDescriptorB;
1564  __IO uint32_t HcRhStatus;
1565  __IO uint32_t HcRhPortStatus1;
1566  __IO uint32_t HcRhPortStatus2;
1567  uint32_t RESERVED0[40];
1568  __I uint32_t Module_ID;
1569 /*------------------------ USB OTG Controller -------------------------------*/
1570 /*#define OTG_INT_STAT (*(REG32*)(USBOTG_BASE + 0x00))
1571 #define OTG_INT_EN (*(REG32*)(USBOTG_BASE + 0x04))
1572 #define OTG_INT_SET (*(REG32*)(USBOTG_BASE + 0x08))
1573 #define OTG_INT_CLR (*(REG32*)(USBOTG_BASE + 0x0C))
1574  On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL
1575 #define OTG_STAT_CTRL (*(REG32*)(USBOTG_BASE + 0x10))
1576 #define USBPortSel (*(REG32*)(USBOTG_BASE + 0x10))
1577 #define OTG_TIMER (*(REG32*)(USBOTG_BASE + 0x14))
1578 */
1579  __I uint32_t OTGIntSt;
1580  __IO uint32_t OTGIntEn;
1581  __O uint32_t OTGIntSet;
1582  __O uint32_t OTGIntClr;
1583  __IO uint32_t OTGStCtrl;/* USBPortSel*/
1584  __IO uint32_t OTGTmr;
1585  uint32_t RESERVED1[58];
1586 /*------ USB Device Interrupt Registers --------------------- */
1587 /*
1588 #define DEV_INT_STAT (*(REG32*)(USB_BASE + 0x00))
1589 #define DEV_INT_EN (*(REG32*)(USB_BASE + 0x04))
1590 #define DEV_INT_CLR (*(REG32*)(USB_BASE + 0x08))
1591 #define DEV_INT_SET (*(REG32*)(USB_BASE + 0x0C))
1592 #define DEV_INT_PRIO (*(REG32*)(USB_BASE + 0x2C)) --> USBDevIntPri
1593 */
1594  __I uint32_t USBDevIntSt;
1595  __IO uint32_t USBDevIntEn;
1596  __O uint32_t USBDevIntClr;
1597  __O uint32_t USBDevIntSet;
1598 /*------ USB Device Command Reagisters ---------------------- */
1599 /*#define CMD_CODE (*(REG32*)(USB_BASE + 0x10))
1600 #define CMD_DATA (*(REG32*)(USB_BASE + 0x14))
1601 */
1602  __O uint32_t USBCmdCode;
1603  __I uint32_t USBCmdData;
1604 /*------ USB Device Data Transfer Registers ----------------- */
1605 /*#define RX_DATA (*(REG32*)(USB_BASE + 0x18))
1606 #define TX_DATA (*(REG32*)(USB_BASE + 0x1C))
1607 #define RX_PLENGTH (*(REG32*)(USB_BASE + 0x20))
1608 #define TX_PLENGTH (*(REG32*)(USB_BASE + 0x24))
1609 #define USB_CTRL (*(REG32*)(USB_BASE + 0x28))
1610 */
1611  __I uint32_t USBRxData;
1612  __O uint32_t USBTxData;
1613  __I uint32_t USBRxPLen;
1614  __O uint32_t USBTxPLen;
1615  __IO uint32_t USBCtrl;
1616  __O uint32_t USBDevIntPri;
1617 /*------ USB Device Endpoint Interrupt Registers ------------- */
1618 /*#define EP_INT_STAT (*(REG32*)(USB_BASE + 0x30))
1619 #define EP_INT_EN (*(REG32*)(USB_BASE + 0x34))
1620 #define EP_INT_CLR (*(REG32*)(USB_BASE + 0x38))
1621 #define EP_INT_SET (*(REG32*)(USB_BASE + 0x3C))
1622 #define EP_INT_PRIO (*(REG32*)(USB_BASE + 0x40))
1623 */
1624  __I uint32_t USBEpIntSt;
1625  __IO uint32_t USBEpIntEn;
1626  __O uint32_t USBEpIntClr;
1627  __O uint32_t USBEpIntSet;
1628  __O uint32_t USBEpIntPri;
1629 /*------ USB Device Endpoint Realization Registers ---------- */
1630 /*#define REALIZE_EP (*(REG32*)(USB_BASE + 0x44))
1631 #define EP_INDEX (*(REG32*)(USB_BASE + 0x48))
1632 #define MAXPACKET_SIZE (*(REG32*)(USB_BASE + 0x4C))
1633 */
1634  __IO uint32_t USBReEp;
1635  __O uint32_t USBEpInd;
1636  __IO uint32_t USBMaxPSize;
1637 /*------------------------ USB Device DMA Registers -----------*/
1638 /*#define DMA_REQ_STAT (*(REG32*)(USB_BASE + 0x50))
1639 #define DMA_REQ_CLR (*(REG32*)(USB_BASE + 0x54))
1640 #define DMA_REQ_SET (*(REG32*)(USB_BASE + 0x58))
1641 #define UDCA_HEAD (*(REG32*)(USB_BASE + 0x80))
1642 #define EP_DMA_STAT (*(REG32*)(USB_BASE + 0x84))
1643 #define EP_DMA_EN (*(REG32*)(USB_BASE + 0x88))
1644 #define EP_DMA_DIS (*(REG32*)(USB_BASE + 0x8C))
1645 #define DMA_INT_STAT (*(REG32*)(USB_BASE + 0x90))
1646 #define DMA_INT_EN (*(REG32*)(USB_BASE + 0x94))
1647 #define EOT_INT_STAT (*(REG32*)(USB_BASE + 0xA0))
1648 #define EOT_INT_CLR (*(REG32*)(USB_BASE + 0xA4))
1649 #define EOT_INT_SET (*(REG32*)(USB_BASE + 0xA8))
1650 #define NDD_REQ_INT_STAT (*(REG32*)(USB_BASE + 0xAC))
1651 #define NDD_REQ_INT_CLR (*(REG32*)(USB_BASE + 0xB0))
1652 #define NDD_REQ_INT_SET (*(REG32*)(USB_BASE + 0xB4))
1653 #define SYS_ERR_INT_STAT (*(REG32*)(USB_BASE + 0xB8))
1654 #define SYS_ERR_INT_CLR (*(REG32*)(USB_BASE + 0xBC))
1655 #define SYS_ERR_INT_SET (*(REG32*)(USB_BASE + 0xC0))*/
1656  __I uint32_t USBDMARSt;
1657  __O uint32_t USBDMARClr;
1658  __O uint32_t USBDMARSet;
1659  uint32_t RESERVED2[9];
1660  __IO uint32_t USBUDCAH;
1661  __I uint32_t USBEpDMASt;
1662  __O uint32_t USBEpDMAEn;
1663  __O uint32_t USBEpDMADis;
1664  __I uint32_t USBDMAIntSt;
1665  __IO uint32_t USBDMAIntEn;
1666  uint32_t RESERVED3[2];
1667  __I uint32_t USBEoTIntSt;
1668  __O uint32_t USBEoTIntClr;
1669  __O uint32_t USBEoTIntSet;
1670  __I uint32_t USBNDDRIntSt;
1671  __O uint32_t USBNDDRIntClr;
1672  __O uint32_t USBNDDRIntSet;
1673  __I uint32_t USBSysErrIntSt;
1674  __O uint32_t USBSysErrIntClr;
1675  __O uint32_t USBSysErrIntSet;
1676  uint32_t RESERVED4[15];
1677 /* USB OTG I2C Registers
1678 #define OTG_I2C_RX (*(REG32*)(USBOTG_I2C_BASE + 0x00))
1679 #define OTG_I2C_TX (*(REG32*)(USBOTG_I2C_BASE + 0x00))
1680 #define OTG_I2C_STS (*(REG32*)(USBOTG_I2C_BASE + 0x04))
1681 #define OTG_I2C_CTL (*(REG32*)(USBOTG_I2C_BASE + 0x08))
1682 #define OTG_I2C_CLKHI (*(REG32*)(USBOTG_I2C_BASE + 0x0C))
1683 #define OTG_I2C_CLKLO (*(REG32*)(USBOTG_I2C_BASE + 0x10))
1684 */
1685  union {
1686  __I uint32_t I2C_RX;
1687  __O uint32_t I2C_TX;
1688  }; /* \todo !!!!!!!!!!!!! It is cleared by writing a one to bit of
1689 the status register. It is unaffected by slave transactions. ????? */
1690  __IO uint32_t I2C_STS;
1691  __IO uint32_t I2C_CTL;
1692  __IO uint32_t I2C_CLKHI;
1693  __O uint32_t I2C_CLKLO;
1694  uint32_t RESERVED5[824];
1695 
1696  /* USB Clock Control Registers */
1697 /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
1698 OTG_CLK_CTRL and OTG_CLK_STAT respectively.
1699 #define USBClkCtrl (*(REG32*)(USBOTG_CLK_BASE + 0x04))
1700 #define USBClkSt (*(REG32*)(USBOTG_CLK_BASE + 0x08))
1701 #define OTG_CLK_CTRL (*(REG32*)(USBOTG_CLK_BASE + 0x04))
1702 #define OTG_CLK_STAT (*(REG32*)(USBOTG_CLK_BASE + 0x08))*/
1703  union {
1704  __IO uint32_t USBClkCtrl;
1705  __IO uint32_t OTGClkCtrl;
1706  };
1707  union {
1708  __I uint32_t USBClkSt;
1709  __I uint32_t OTGClkSt;
1710  };
1711 } LPC_USB_TypeDef;
1712 
1713 
1714 
1715 /*------ ТИПЫ ДАННЫХ - DATA TYPES --------------------------------------------*/
1716 #if defined ( __CC_ARM )
1717 #pragma no_anon_unions
1718 #endif
1719 
1720 #include "nxp_base_addresses.h"
1721 
1722 #define VIC ((VIC_TypeDef *) VIC_BASE )
1723 
1724 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
1725 
1726 #define LPC_IO ((LPC_IO_TypeDef_old *) LPC_GPIO_BASE )
1727 #define LPC_IO0 ((LPC_IO_TypeDef_old *) LPC_GPIO_BASE )
1728 #define LPC_IO1 ((LPC_IO_TypeDef_old *) LPC_GPIO_BASE + 0x10)
1729 
1730 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
1731 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
1732 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
1733 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
1734 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
1735 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
1736 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
1737 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
1738 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
1739 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
1740 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
1741 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
1742 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
1743 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
1744 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
1745 #define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
1746 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
1747 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
1748 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
1749 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
1750 
1751 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
1752 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
1753 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
1754 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINSEL_BASE )
1755 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
1756 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
1757 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_AD0_BASE )
1758 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
1759 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
1760 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
1761 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
1762 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
1763 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
1764 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
1765 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
1766 
1767 #if (i_MCU_MODEL >= 2300)
1768 
1769 #define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
1770 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
1771 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
1772 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
1773 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
1774 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
1775 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
1776 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
1777 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
1778 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
1779 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
1780 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
1781 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USBHC_BASE)
1782 #if (i_MCU_MODEL >= 2420)
1783 #define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
1784 #endif
1785 #endif
1786 
1787 /**
1788  * @}
1789  */
1790 /*--------------HERE THERE IS SOME INLINE FUNCTIONS ------------------*/
1791 
1792 
1793 
1794 
1795 #ifndef NULL
1796  #if defined(__cplusplus)
1797  #define NULL 0
1798  #else
1799  #define NULL ((void *)0)
1800  #endif
1801 #endif
1802 /** \addtogroup LPC2xxx_System
1803  * @{
1804  */
1805 extern const ISR_ptr_type ISR_HANDLES_ARRAY[];
1806 extern const char sizeof_ISR_HANDLES_ARRAY;
1807 
1808 __STATIC_INLINE ISR_ptr_type GET_ISR_HANDLER_BY_NUMBER(const IRQn_Type IRQn )
1809 {
1810  if ((unsigned char)IRQn < sizeof_ISR_HANDLES_ARRAY)
1811  return ISR_HANDLES_ARRAY[IRQn];
1812  else
1813  return NULL;
1814 };
1815 /** \brief Set Interrupt Priority
1816 
1817  The function sets the priority of an interrupt.
1818 
1819  \note The priority cannot be set for every core interrupt.
1820 
1821  \param [in] IRQn Interrupt number.
1822  \param [in] priority Priority to set.
1823  */
1824 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1825 {
1826 ISR_ptr_type isr_func;
1827  //isr_func = GET_ISR_HANDLER_BY_NUMBER(IRQn);
1828  //if (isr_func != NULL)
1829  if ((unsigned char)IRQn < sizeof_ISR_HANDLES_ARRAY)
1830  VIC->VectCntl[IRQn] = priority & 0xF;
1831 }
1832 
1833 /** \brief Enable External Interrupt
1834 
1835  The function enables a device-specific interrupt in the NVIC interrupt controller.
1836 
1837  \param [in] IRQn External interrupt number. Value cannot be negative.
1838  */
1839 void NVIC_EnableIRQ(IRQn_Type IRQn);
1840 
1841 /** \brief Disable External Interrupt
1842 
1843  The function enables a device-specific interrupt in the NVIC interrupt controller.
1844 
1845  \param [in] IRQn External interrupt number. Value cannot be negative.
1846  */
1847 //#define NVIC_DisableIRQ(IRQn) SystemVIC_SetISR(NULL,IRQn,-1)
1848 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1849 {
1850  VIC->IntEnClr = 1 << IRQn;
1851 }
1852 
1853 /*------ СПИСОК ГЛОБАЛЬНЫХ ФУНЦИЙ - PUBLIC LIST API --------------------------*/
1854 
1855 
1856 /** \brief Set Priority Grouping
1857 
1858  The function only for compatibility PriorityGroup == 7 is supported only
1859 
1860  \param [in] PriorityGroup Priority grouping field.
1861  */
1862 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1863 {
1864 
1865 }
1866 
1867 
1868 /** \brief Get Priority Grouping
1869 
1870  The function only for compatibility PriorityGroup == 7 is supported only
1871 
1872  \return Always 7
1873  */
1874 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1875 {
1876  return (7);
1877 }
1878 
1879 /** @} end of group LPC2xxx_System */
1880 
1881 
1882 /**\defgroup LPC2xxx_System_periphiral LPC2xxx System etc periphirals
1883  * \ingroup LPC2xxx_System
1884  */
1885 #endif /* _ARCH_ARM_NXP_LPC2XXX_CMSIS_H_ */