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CMSIS2000
0.0.7
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NXP PLCK divider NXP PCLK Peripheral Clock devider -> PLCK divider (VPB bus clock dividers) Bit1 Bit0 Description 0 0 cclk/4 (1/4 From CPU CLOCK) 0 1 cclk/1 (No division) 1 0 cclk/2 (1/2 From CPU CLOCK) 1 1 cclk/6 or cclk/8. More...
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Files | |
| file | lpc2xxx_pclk.h |
| Definitions for NXP LPC2xxx PLCLK (peripheral) module and POWERMODI:E. | |
| file | lpc2xxx_pconp.h |
| peripheries masks for PCONP | |
| file | lpc2xxx_pllclk.h |
| Definitions for NXP LPC2xxx PLL module. | |
Macros | |
| #define | CLKSRCSEL_concat(a, b) CLKSRCSEL_concat2(CLKSRCSEL_Val_,b) |
| #define | CLKSRCSEL_concat2(a, b) a##b |
| #define | CLKSRCSEL_IRC 0 |
| 00 Selects the Internal RC oscillator as the PLL clock source (default). | |
| #define | CLKSRCSEL_RTC 2 |
| 10 Selects the RTC oscillator as the PLL clock source. | |
| #define | CLKSRCSEL_Val CLKSRCSEL_XTAL /* by default enablin external OSC*/ |
| #define | CLKSRCSEL_Val_0 IRC_OSC_HZ |
| #define | CLKSRCSEL_Val_1 XTAL_HZ |
| #define | CLKSRCSEL_Val_2 RTC_CLK_HZ |
| #define | CLKSRCSEL_XTAL 1 |
| 01 Selects the main oscillator as the PLL clock source. | |
| #define | F_CCLK_HZ ((PLL_MValue + 1) * F_OSC_HZ) |
| Defenitions for Phased Lock Loop (PLL) | |
| #define | F_CCO_HZ (2 * (1 << PLL_PValue) * F_CCLK_HZ) |
| #define | F_OSC_HZ CLKSRCSEL_concat(,CLKSRCSEL_Val) |
| there is three clock soursec in lpc2xxx and table here describe sourses and frequency constants. | |
| #define | IRC_OSC_HZ (4000000UL)/* Internal RC oscillator frequency*/ |
| #define | RTC_CLK_HZ (32768U)/* external RTC oscillator frequency*/ |
NXP PLCK divider NXP PCLK Peripheral Clock devider -> PLCK divider (VPB bus clock dividers) Bit1 Bit0 Description 0 0 cclk/4 (1/4 From CPU CLOCK) 0 1 cclk/1 (No division) 1 0 cclk/2 (1/2 From CPU CLOCK) 1 1 cclk/6 or cclk/8.
| #define CLKSRCSEL_concat | ( | a, | |
| b | |||
| ) | CLKSRCSEL_concat2(CLKSRCSEL_Val_,b) |
Definition at line 72 of file lpc2xxx_pllclk.h.
| #define CLKSRCSEL_concat2 | ( | a, | |
| b | |||
| ) | a##b |
Definition at line 71 of file lpc2xxx_pllclk.h.
| #define CLKSRCSEL_IRC 0 |
00 Selects the Internal RC oscillator as the PLL clock source (default).
Definition at line 58 of file lpc2xxx_pllclk.h.
| #define CLKSRCSEL_RTC 2 |
10 Selects the RTC oscillator as the PLL clock source.
Definition at line 60 of file lpc2xxx_pllclk.h.
| #define CLKSRCSEL_Val CLKSRCSEL_XTAL /* by default enablin external OSC*/ |
Definition at line 63 of file lpc2xxx_pllclk.h.
| #define CLKSRCSEL_Val_0 IRC_OSC_HZ |
Definition at line 67 of file lpc2xxx_pllclk.h.
| #define CLKSRCSEL_Val_1 XTAL_HZ |
Definition at line 68 of file lpc2xxx_pllclk.h.
| #define CLKSRCSEL_Val_2 RTC_CLK_HZ |
Definition at line 69 of file lpc2xxx_pllclk.h.
| #define CLKSRCSEL_XTAL 1 |
01 Selects the main oscillator as the PLL clock source.
Definition at line 59 of file lpc2xxx_pllclk.h.
| #define F_CCLK_HZ ((PLL_MValue + 1) * F_OSC_HZ) |
Defenitions for Phased Lock Loop (PLL)
Definition at line 122 of file lpc2xxx_pllclk.h.
| #define F_CCO_HZ (2 * (1 << PLL_PValue) * F_CCLK_HZ) |
Definition at line 123 of file lpc2xxx_pllclk.h.
| #define F_OSC_HZ CLKSRCSEL_concat(,CLKSRCSEL_Val) |
there is three clock soursec in lpc2xxx and table here describe sourses and frequency constants.
CLKSRCSEL_IRC 0 IRC_OSC_HZ will be select as osc source CLKSRCSEL_XTAL 1 XTAL_HZ will be select as osc source CLKSRCSEL_RTC 2 RTC_CLK_HZ will be select as osc source
Definition at line 88 of file lpc2xxx_pllclk.h.
| #define IRC_OSC_HZ (4000000UL)/* Internal RC oscillator frequency*/ |
Definition at line 53 of file lpc2xxx_pllclk.h.
| #define RTC_CLK_HZ (32768U)/* external RTC oscillator frequency*/ |
Definition at line 56 of file lpc2xxx_pllclk.h.