bsp_board_olimex_H2103.h File Reference

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Macros
#define	BSP_BOARD_HAS_UART0   1
#define	BSP_BOARD_HAS_UART1   1
#define	bsp_board_olimex_H2103   1
#define	i_ARCH   ARM7
#define	i_BOARD   olimex_H2103
#define	i_MCU_FAMILY   LPC2xxx
#define	i_MCU_MODEL   2103
#define	i_VENDOR   olimex
#define	i_VERSION   0x010000
#define	PCLK_DIVIDER   4
#define	PLL_MValue   3
#define	PLL_PValue   1
#define	XTAL_HZ   14745600UL
	Setting the Phased Lock Loop (PLL) for Olimex LPC-H2103 14.7456 MHz crystal.

Macro Definition Documentation

#define BSP_BOARD_HAS_UART0   1

Definition at line 51 of file bsp_board_olimex_H2103.h.

#define BSP_BOARD_HAS_UART1   1

Definition at line 52 of file bsp_board_olimex_H2103.h.

#define bsp_board_olimex_H2103   1

Definition at line 36 of file bsp_board_olimex_H2103.h.

#define i_ARCH   ARM7

Definition at line 39 of file bsp_board_olimex_H2103.h.

#define i_BOARD   olimex_H2103

Definition at line 45 of file bsp_board_olimex_H2103.h.

#define i_MCU_FAMILY   LPC2xxx

Definition at line 41 of file bsp_board_olimex_H2103.h.

#define i_MCU_MODEL   2103

Definition at line 43 of file bsp_board_olimex_H2103.h.

#define i_VENDOR   olimex

Definition at line 47 of file bsp_board_olimex_H2103.h.

#define i_VERSION   0x010000

Definition at line 49 of file bsp_board_olimex_H2103.h.

#define PCLK_DIVIDER   4

Definition at line 107 of file bsp_board_olimex_H2103.h.

#define PLL_MValue   3

Definition at line 103 of file bsp_board_olimex_H2103.h.

#define PLL_PValue   1

Definition at line 104 of file bsp_board_olimex_H2103.h.

#define XTAL_HZ   14745600UL

Setting the Phased Lock Loop (PLL) for Olimex LPC-H2103 14.7456 MHz crystal.

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Olimex LPC-H2103 has a 14.7456 mhz crystal

We'd like the LPC2106 to run at 53.2368 mhz (has to be an even multiple of crystal)

According to the Philips LPC2106 manual: M = cclk / Fosc where: M = PLL multiplier (bits 0-4 of PLLCFG) cclk = 53236800 hz Fosc = 14745600 hz

Solving: M = 53236800 / 14745600 = 3.6103515625 M = 4 (round up)

*Note: M - 1 must be entered into bits 0-4 of PLLCFG (assign 3 to these bits)

The Current Controlled Oscilator (CCO) must operate in the range 156 mhz to 320 mhz

According to the Philips LPC2106 manual: Fcco = cclk * 2 * P where: Fcco = CCO frequency cclk = 53236800 hz P = PLL divisor (bits 5-6 of PLLCFG)

Solving: Fcco = 53236800 * 2 * P P = 2 (trial value) Fcco = 53236800 * 2 * 2 Fcc0 = 212947200 hz (good choice for P since it's within the 156 mhz to 320 mhz range

From Table 19 (page 48) of Philips LPC2106 manual P = 2, PLLCFG bits 5-6 = 1 (assign 1 to these bits)

Finally: PLLCFG = 0 01 00011 = 0x23

Final note: to load PLLCFG register, we must use the 0xAA followed 0x55 write sequence to the PLLFEED register this is done in the short function feed() below

Definition at line 96 of file bsp_board_olimex_H2103.h.