CMSIS is Cortex Microcontroller Software Interface Standard

ARM provides as part of the CMSIS the following software layers that are available for various compiler implementations:

Core Peripheral Access Layer: contains name definitions, address definitions and helper functions to access core registers and peripherals. It defines also a device independent interface for RTOS Kernels that includes debug channel definitions.

These software layers are expanded by Silicon partners with:

Device Peripheral Access Layer: provides definitions for all device peripherals
Access Functions for Peripherals (optional): provides additional helper functions for peripherals

CMSIS defines for a Cortex-M Microcontroller System:

A common way to access peripheral registers and a common way to define exception vectors.
The register names of the Core Peripherals and the names of the Core Exception Vectors.
An device independent interface for RTOS Kernels including a debug channel.

By using CMSIS compliant software components, the user can easier re-use template code. CMSIS is intended to enable the combination of software components from multiple middleware vendors.

Coding Rules and Conventions

Essentials

The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, there are disable and enable sequences for PC-LINT inserted.

ANSI standard data types defined in the ANSI C header file <stdint.h> are used.

#define constants that include expressions must be enclosed by parenthesis.

Variables and parameters have a complete data type.

All functions in the Core Peripheral Access Layer are re-entrant.

The Core Peripheral Access Layer has no blocking code (which means that wait/query loops are done at other software layers).

For each exception/interrupt there is definition for:
- an exception/interrupt handler with the postfix _Handler (for exceptions) or _IRQHandler (for interrupts).
- a default exception/interrupt handler (weak definition) that contains an endless loop.
- a #define of the interrupt number with the postfix _IRQn.

Recommendations

The CMSIS recommends the following conventions for identifiers.

CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
CamelCase names to identify peripherals access functions and interrupts.
PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
Doxygen comments for all functions are included as described under Function Comments below.

Comments

Comments use the ANSI C90 style (/ * comment * /) or C++ style (// comment). It is assumed that the programming tools support today consistently the C++ comment style.
Function Comments provide for each function the following information:
- one-line brief function overview.
- detailed parameter explanation.
- detailed information about return values.
- detailed description of the actual function.
Doxygen Example:

      /**
       * @brief  Enable Interrupt in NVIC Interrupt Controller
       * @param  IRQn  interrupt number that specifies the interrupt
       * @return none.
       * Enable the specified interrupt in the NVIC Interrupt Controller.
       * Other settings of the interrupt such as priority are not affected.
       */

/**

Data Types and IO Type Qualifiers in CMSIS

The Cortex-M HAL uses the standard types from the standard ANSI C header file <stdint.h>. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers.

IO Type Qualifier	#define	description
__I	volatile const	Read access only
__O	volatile	Write access only
__IO	volatile	Read and write access

CMSIS Version Number

Files core_cm0.h, core_cm3.h, core_cm4.h contains the version number of the CMSIS with the following define:

core_cm0.h:

#define __CM0_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       * /
#define __CM0_CMSIS_VERSION_SUB   (0x00)      /* [15:0]  sub version        * /
#define __CM1_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB)

core_cm3.h:

#define __CM3_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       * /
#define __CM3_CMSIS_VERSION_SUB   (0x00)      /* [15:0]  sub version        * /
#define __CM3_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB)

core_cm4.h:

#define __CM4_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       * /
#define __CM4_CMSIS_VERSION_SUB   (0x00)      /* [15:0]  sub version        * /
#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB)

CMSIS Cortex Core

Files core_cm0.h, core_cm3.h, core_cm4.h contains the type of the CMSIS Cortex-M with the following defines:

core_cm0.h:

#define __CORTEX_M (0x00)

core_cm3.h:

#define __CORTEX_M (0x03)

core_cm4.h:

#define __CORTEX_M (0x04)

CMSIS Files

This section describes the Files provided in context with the CMSIS to access the Cortex-M hardware and peripherals.

File	Provider	Description
device.h	Device specific (provided by silicon partner)	Defines the peripherals for the actual device. The file may use several other include files to define the peripherals of the actual device.
core_cm0.h	ARM (for RealView ARMCC, IAR, and GNU GCC)	Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.h	ARM (for RealView ARMCC, IAR, and GNU GCC)	Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm4.h	ARM (for RealView ARMCC, IAR, and GNU GCC)	Defines the core peripherals for the Cortex-M4 CPU and core peripherals.
core_cm4_simd.h	ARM (for RealView ARMCC, IAR, and GNU GCC)	Defines the Cortex-M4 Core SIMD functions.
core_cmFunc.h	ARM (for RealView ARMCC, IAR, and GNU GCC)	Defines the Cortex-M Core Register access functions.
core_cmInstr.h	ARM (for RealView ARMCC, IAR, and GNU GCC)	Defines the Cortex-M Core instructions.
core_cm0.c	ARM (for RealView ARMCC, IAR, and GNU GCC)	Provides helper functions that access core registers.
core_cm3.c	ARM (for RealView ARMCC, IAR, and GNU GCC)	Provides helper functions that access core registers.
core_cm4.c	ARM (for RealView ARMCC, IAR, and GNU GCC)	Provides helper functions that access core registers.
startup_device	ARM (adapted by compiler partner / silicon partner)	Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
system_device	ARM (adapted by silicon partner)	Provides a device specific configuration file for the device. It configures the device initializes typically the oscillator (PLL) that is part of the microcontroller device

device.h file

The file device.h is provided by the silicon vendor and is the central include file that the application programmer is using in the C source code. This file contains:

Interrupt Number Definition: provides interrupt numbers (IRQn) for all core and device specific exceptions and interrupts.
Configuration for core_cm0.h / core_cm3.h / core_cm4.h: reflects the actual configuration of the Cortex-M processor that is part of the actual device. As such the file core_cm0.h / core_cm3.h / core_cm4.h is included that implements access to processor registers and core peripherals.
Device Peripheral Access Layer: provides definitions for all device peripherals. It contains all data structures and the address mapping for the device specific peripherals.
Access Functions for Peripherals (optional): provides additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device specific library provided by the silicon vendor.

Interrupt Number Definition

To access the device specific interrupts the device.h file defines IRQn numbers for the complete device using a enum typedef as shown below:

typedef enum IRQn
{
/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
  HardFault_IRQn                  = -13,      /*!< 3 Cortex-M3 Hard Fault Interrupt                      */
  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
/******  STM32 specific Interrupt Numbers ****************************************************************/
  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
  :
  :
  } IRQn_Type;

Device Specific Defines

The following device implementation specific defines are set in the device header file and are used for the Cortex-M core configuration options. Some configuration options are reflected in the CMSIS layer using the #define settings described below.

Several features in core_cm#.h are configured by the following defines that must be defined before include <core_cm#.h> preprocessor command. If the defines are missing the default values will be used.

#define	Core	Value	Default	Description
__CM0_REV	M0	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__CM3_REV	M3	0x0101 \| 0x0200	0x0200	Core revision number ([15:8] revision number, [7:0] patch number)
__CM4_REV	M4	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS	M0, M3, M4	2 .. 8	2 (M0) 4 (CM3, CM4)	Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT	M0, M3, M4	0 \| 1	0	Defines if a MPU is present or not
__FPU_PRESENT	M4	0 \| 1	0	Defines if a FPU is present or not
__Vendor_SysTickConfig	M0, M3, M4	0 \| 1	0	When this define is setup to 1, the SysTickConfig function in core_cm3.h is excluded. In this case the device.h file must contain a vendor specific implementation of this function.

Device Peripheral Access Layer

Each peripheral uses a prefix which consists of <device abbreviation>_ and <peripheral name>_ to identify peripheral registers that access this specific peripheral. The intention of this is to avoid name collisions caused due to short names. If more than one peripheral of the same type exists, identifiers have a postfix (digit or letter). For example:

<device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.

typedef struct
{
  union {
  __I  uint8_t  RBR;                     /*!< Offset: 0x000 (R/ )  Receiver Buffer Register    */
  __O  uint8_t  THR;                     /*!< Offset: 0x000 ( /W)  Transmit Holding Register   */
  __IO uint8_t  DLL;                     /*!< Offset: 0x000 (R/W)  Divisor Latch LSB           */
       uint32_t RESERVED0;
  };
  union {
  __IO uint8_t  DLM;                     /*!< Offset: 0x004 (R/W)  Divisor Latch MSB           */
  __IO uint32_t IER;                     /*!< Offset: 0x004 (R/W)  Interrupt Enable Register   */
  };
  union {
  __I  uint32_t IIR;                     /*!< Offset: 0x008 (R/ )  Interrupt ID Register       */
  __O  uint8_t  FCR;                     /*!< Offset: 0x008 ( /W)  FIFO Control Register       */
  };
  __IO uint8_t  LCR;                     /*!< Offset: 0x00C (R/W)  Line Control Register       */
       uint8_t  RESERVED1[7];
  __I  uint8_t  LSR;                     /*!< Offset: 0x014 (R/ )  Line Status Register        */
       uint8_t  RESERVED2[7];
  __IO uint8_t  SCR;                     /*!< Offset: 0x01C (R/W)  Scratch Pad Register        */
       uint8_t  RESERVED3[3];
  __IO uint32_t ACR;                     /*!< Offset: 0x020 (R/W)  Autobaud Control Register   */
  __IO uint8_t  ICR;                     /*!< Offset: 0x024 (R/W)  IrDA Control Register       */
       uint8_t  RESERVED4[3];
  __IO uint8_t  FDR;                     /*!< Offset: 0x028 (R/W)  Fractional Divider Register */
       uint8_t  RESERVED5[7];
  __IO uint8_t  TER;                     /*!< Offset: 0x030 (R/W)  Transmit Enable Register    */
       uint8_t  RESERVED6[39];
  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058 (R/ )  FIFO Level Register         */
} LPC_UART_TypeDef;

<device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. For example UART1->DR is the data register of UART1.

#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )

#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )

Minimal Requiements

To access the peripheral registers and related function in a device the files device.h and core_cm0.h / core_cm3.h defines as a minimum:

The Register Layout Typedef for each peripheral that defines all register names. Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of the peripheral registers. For example:

typedef struct
{
  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
} SysTick_Type;

Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined). For example:

#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */

Access Definition for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple access definitions exist, i.e. LPC_UART0, LPC_UART2). For Example:

#define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */

These definitions allow to access the peripheral registers from user code with simple assignments like:

SysTick->CTRL = 0;

Optional Features

In addition the device.h file may define:

#define constants that simplify access to the peripheral registers. These constant define bit-positions or other specific patterns are that required for the programming of the peripheral registers. The identifiers used start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for such #define constants.
Functions that perform more complex functions with the peripheral (i.e. status query before a sending register is accessed). Again these function start with <device abbreviation>_ and <peripheral name>_.

core_cm0.h, core_cm0.c

File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers and core peripherals with efficient functions (defined as static inline).

File core_cm0.c defines several helper functions that access processor registers.

Together these files implement the Core Peripheral Access Layer for a Cortex-M0.

The define __CMSIS_GENERIC allows to use core_cm0.h in generic library projects that are device independent. Only core relevant types and defines are used.

core_cm3.h, core_cm3.c

File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers and core peripherals with efficient functions (defined as static inline).

File core_cm3.c defines several helper functions that access processor registers.

Together these files implement the Core Peripheral Access Layer for a Cortex-M3.

The define __CMSIS_GENERIC allows to use core_cm3.h in generic library projects that are device independent. Only core relevant types and defines are used.

core_cm4.h, core_cm4.c, core_cm4_simd.h

File core_cm4.h describes the data structures for the Cortex-M4 core peripherals and does the address mapping of this structures. It also provides basic access to the Cortex-M4 core registers and core peripherals with efficient functions (defined as static inline).

File core_cm4.c defines helper functions that access processor registers.

File core_cm4_simd.h defines Cortex-M4 SIMD instructions.

Together these files implement the Core Peripheral Access Layer for a Cortex-M4.

The define __CMSIS_GENERIC allows to use core_cm4.h in generic library projects that are device independent. Only core relevant types and defines are used.

core_cmFunc.h and core_cmInstr.h

File core_cmFunc.h defines the Cortex-M Core Register access functions (defined as static inline)..

File core_cmInstr.h defines the Cortex-M Core instructions (defined as static inline)..

These files are part of the Core Peripheral Access Layer for a Cortex-M.

Startup_device

A template file for startup_device is provided by ARM for each supported compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific interrupt handlers. Each interrupt handler is defined as weak function to an dummy handler. Therefore the interrupt handler can be directly used in application software without any requirements to adapt the startup_device file.

The following exception names are fixed and define the start of the vector table for a Cortex-M0:

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     SVC_Handler               ; SVCall Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     PendSV_Handler            ; PendSV Handler
                DCD     SysTick_Handler           ; SysTick Handler

The following exception names are fixed and define the start of the vector table for a Cortex-M3:

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     MemManage_Handler         ; MPU Fault Handler
                DCD     BusFault_Handler          ; Bus Fault Handler
                DCD     UsageFault_Handler        ; Usage Fault Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     SVC_Handler               ; SVCall Handler
                DCD     DebugMon_Handler          ; Debug Monitor Handler
                DCD     0                         ; Reserved
                DCD     PendSV_Handler            ; PendSV Handler
                DCD     SysTick_Handler           ; SysTick Handler

In the following examples for device specific interrupts are shown:

; External Interrupts
                DCD     WWDG_IRQHandler           ; Window Watchdog
                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
                DCD     TAMPER_IRQHandler         ; Tamper

Device specific interrupts must have a dummy function that can be overwritten in user code. Below is an example for this dummy function.

Default_Handler PROC
                EXPORT WWDG_IRQHandler   [WEAK]
                EXPORT PVD_IRQHandler    [WEAK]
                EXPORT TAMPER_IRQHandler [WEAK]
                :
                :
                WWDG_IRQHandler
                PVD_IRQHandler
                TAMPER_IRQHandler
                :
                :
                B .
                ENDP

The user application may simply define an interrupt handler function by using the handler name as shown below.

void WWDG_IRQHandler(void)
{
  :
  :
}

/**

system_device.с file

A template file for system_device.c is provided by ARM but adapted by the silicon vendor to match their actual device. As a minimum requirement this file must provide a device specific system configuration function and a global variable that contains the system frequency. It configures the device and initializes typically the oscillator (PLL) that is part of the microcontroller device.

The file system_device.c must provide as a minimum requirement the SystemInit function as shown below.

Function Definition

Description

void SystemInit (void)

Setup the microcontroller system. Typically this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with variable clock speed it also updates the variable SystemCoreClock. SystemInit is called from startup_device file.

void SystemCoreClockUpdate (void)

Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates the current core clock.

Also part of the file system_device.c is the variable SystemCoreClock which contains the current CPU clock speed shown below.

Variable Definition

Description

uint32_t SystemCoreClock (void)

Contains the system core clock (which is the system clock frequency supplied to the SysTick timer and the processor core clock). This variable can be used by the user application to setup the SysTick timer or configure other parameters. It may also be used by debugger to query the frequency of the debug timer or configure the trace clock speed. SystemCoreClock is initialized with a correct predefined value.

The compiler must be configured to avoid the removal of this variable in case that the application program is not using it. It is important for debug systems that the variable is physically present in memory so that it can be examined to configure the debugger.

Note:

The above definitions are the minimum requirements for the file system_device.c. This file may export more functions or variables that provide a more flexible configuration of the microcontroller system.