enum | IRQn {
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
SVCall_IRQn = -5,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
WDT_IRQn = 0,
RTC_IRQn = 1,
TIM0_IRQn = 2,
TIM2_IRQn = 3,
MCIA_IRQn = 4,
MCIB_IRQn = 5,
UART0_IRQn = 6,
UART1_IRQn = 7,
UART2_IRQn = 8,
UART4_IRQn = 9,
AACI_IRQn = 10,
CLCD_IRQn = 11,
ENET_IRQn = 12,
USBDC_IRQn = 13,
USBHC_IRQn = 14,
CHLCD_IRQn = 15,
FLEXRAY_IRQn = 16,
CAN_IRQn = 17,
LIN_IRQn = 18,
I2C_IRQn = 19,
CPU_CLCD_IRQn = 28,
UART3_IRQn = 30,
SPI_IRQn = 31,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
SVCall_IRQn = -5,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
WDT_IRQn = 0,
RTC_IRQn = 1,
TIM0_IRQn = 2,
TIM2_IRQn = 3,
MCIA_IRQn = 4,
MCIB_IRQn = 5,
UART0_IRQn = 6,
UART1_IRQn = 7,
UART2_IRQn = 8,
UART4_IRQn = 9,
AACI_IRQn = 10,
CLCD_IRQn = 11,
ENET_IRQn = 12,
USBDC_IRQn = 13,
USBHC_IRQn = 14,
CHLCD_IRQn = 15,
FLEXRAY_IRQn = 16,
CAN_IRQn = 17,
LIN_IRQn = 18,
I2C_IRQn = 19,
CPU_CLCD_IRQn = 28,
UART3_IRQn = 30,
SPI_IRQn = 31,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
WDT_IRQn = 0,
RTC_IRQn = 1,
TIM0_IRQn = 2,
TIM2_IRQn = 3,
MCIA_IRQn = 4,
MCIB_IRQn = 5,
UART0_IRQn = 6,
UART1_IRQn = 7,
UART2_IRQn = 8,
UART4_IRQn = 9,
AACI_IRQn = 10,
CLCD_IRQn = 11,
ENET_IRQn = 12,
USBDC_IRQn = 13,
USBHC_IRQn = 14,
CHLCD_IRQn = 15,
FLEXRAY_IRQn = 16,
CAN_IRQn = 17,
LIN_IRQn = 18,
I2C_IRQn = 19,
CPU_CLCD_IRQn = 28,
UART3_IRQn = 30,
SPI_IRQn = 31,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
WDT_IRQn = 0,
RTC_IRQn = 1,
TIM0_IRQn = 2,
TIM2_IRQn = 3,
MCIA_IRQn = 4,
MCIB_IRQn = 5,
UART0_IRQn = 6,
UART1_IRQn = 7,
UART2_IRQn = 8,
UART4_IRQn = 9,
AACI_IRQn = 10,
CLCD_IRQn = 11,
ENET_IRQn = 12,
USBDC_IRQn = 13,
USBHC_IRQn = 14,
CHLCD_IRQn = 15,
FLEXRAY_IRQn = 16,
CAN_IRQn = 17,
LIN_IRQn = 18,
I2C_IRQn = 19,
CPU_CLCD_IRQn = 28,
UART3_IRQn = 30,
SPI_IRQn = 31,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
SVCall_IRQn = -5,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
WDT_IRQn = 0,
RTC_IRQn = 1,
TIM0_IRQn = 2,
TIM2_IRQn = 3,
MCIA_IRQn = 4,
MCIB_IRQn = 5,
UART0_IRQn = 6,
UART1_IRQn = 7,
UART2_IRQn = 8,
UART4_IRQn = 9,
AACI_IRQn = 10,
CLCD_IRQn = 11,
ENET_IRQn = 12,
USBDC_IRQn = 13,
USBHC_IRQn = 14,
CHLCD_IRQn = 15,
FLEXRAY_IRQn = 16,
CAN_IRQn = 17,
LIN_IRQn = 18,
I2C_IRQn = 19,
CPU_CLCD_IRQn = 28,
UART3_IRQn = 30,
SPI_IRQn = 31,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
WDT_IRQn = 0,
RTC_IRQn = 1,
TIM0_IRQn = 2,
TIM2_IRQn = 3,
MCIA_IRQn = 4,
MCIB_IRQn = 5,
UART0_IRQn = 6,
UART1_IRQn = 7,
UART2_IRQn = 8,
UART4_IRQn = 9,
AACI_IRQn = 10,
CLCD_IRQn = 11,
ENET_IRQn = 12,
USBDC_IRQn = 13,
USBHC_IRQn = 14,
CHLCD_IRQn = 15,
FLEXRAY_IRQn = 16,
CAN_IRQn = 17,
LIN_IRQn = 18,
I2C_IRQn = 19,
CPU_CLCD_IRQn = 28,
UART3_IRQn = 30,
SPI_IRQn = 31,
NonMaskableInt_IRQn = -14,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
WDT_IRQn = 0,
TIMER0_IRQn = 1,
TIMER1_IRQn = 2,
TIMER2_IRQn = 3,
TIMER3_IRQn = 4,
UART0_IRQn = 5,
UART1_IRQn = 6,
UART2_IRQn = 7,
UART3_IRQn = 8,
PWM1_IRQn = 9,
I2C0_IRQn = 10,
I2C1_IRQn = 11,
I2C2_IRQn = 12,
SPI_IRQn = 13,
SSP0_IRQn = 14,
SSP1_IRQn = 15,
PLL0_IRQn = 16,
RTC_IRQn = 17,
EINT0_IRQn = 18,
EINT1_IRQn = 19,
EINT2_IRQn = 20,
EINT3_IRQn = 21,
ADC_IRQn = 22,
BOD_IRQn = 23,
USB_IRQn = 24,
CAN_IRQn = 25,
DMA_IRQn = 26,
I2S_IRQn = 27,
ENET_IRQn = 28,
RIT_IRQn = 29,
MCPWM_IRQn = 30,
QEI_IRQn = 31,
PLL1_IRQn = 32,
USBActivity_IRQn = 33,
CANActivity_IRQn = 34,
WDT_IRQn = 0,
PROGRAMM_INT_IRQn = 1,
ARM_CORE_ICE_RX_IRQn = 2,
ARM_CORE_ICE_TX_IRQn = 3,
TIMER0_IRQn = 4,
TIMER1_IRQn = 5,
UART0_IRQn = 6,
UART1_IRQn = 7,
PWM_IRQn = 8,
PWM0_IRQn = 8,
I2C_IRQn = 9,
I2C0_IRQn = 9,
SPI_IRQn = 10,
SPI0_IRQn = 10,
SSP0_IRQn = 10,
SPI1_IRQn = 11,
SSP1_IRQn = 11,
PLL0_IRQn = 12,
RTC_IRQn = 13,
EINT0_IRQn = 14,
EINT1_IRQn = 15,
EINT2_IRQn = 16,
EINT3_IRQn = 17,
ADC_IRQn = 18,
CAN1_TX = 20,
CAN2_TX_IRQn = 21,
CAN3_TX_IRQn = 22,
CAN4_TX_IRQn = 23,
RESERVE_23_IRQn = 24,
RESERVE_24_IRQn = 25,
CAN1_RX_IRQn = 26,
CAN2_RX_IRQn = 27,
CAN3_RX_IRQn = 28,
CAN4_RX_IRQn = 29
} |