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core_cm3.h
См. документацию.
1 /**************************************************************************//**
2  * @file core_cm3.h
3  * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4  * @version V3.01
5  * @date 22. March 2012
6  *
7  * @note
8  * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9  *
10  * @par
11  * ARM Limited (ARM) is supplying this software for use with Cortex-M
12  * processor based microcontrollers. This file can be freely distributed
13  * within development tools that are supporting such ARM based processors.
14  *
15  * @par
16  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21  *
22  ******************************************************************************/
23 #if defined ( __ICCARM__ )
24  #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 #ifndef __CORE_CM3_H_GENERIC
32 #define __CORE_CM3_H_GENERIC
33 
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35  CMSIS violates the following MISRA-C:2004 rules:
36 
37  \li Required Rule 8.5, object/function definition in header file.<br>
38  Function definitions in header files are used to allow 'inlining'.
39 
40  \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41  Unions are used for effective representation of core registers.
42 
43  \li Advisory Rule 19.7, Function-like macro defined.<br>
44  Function-like macros are used to allow more efficient code.
45  */
46 
47 
48 /*******************************************************************************
49  * CMSIS definitions
50  ******************************************************************************/
51 /** \ingroup Cortex_M3
52  @{
53  */
54 
55 /* CMSIS CM3 definitions */
56 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
58 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
59  __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
60 
61 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
62 
63 
64 #if defined ( __CC_ARM )
65  #define __ASM __asm /*!< asm keyword for ARM Compiler */
66  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67  #define __STATIC_INLINE static __inline
68 
69 #elif defined ( __ICCARM__ )
70  #define __ASM __asm /*!< asm keyword for IAR Compiler */
71  #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72  #define __STATIC_INLINE static inline
73 
74 #elif defined ( __TMS470__ )
75  #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
76  #define __STATIC_INLINE static inline
77 
78 #elif defined ( __GNUC__ )
79  #define __ASM __asm /*!< asm keyword for GNU Compiler */
80  #define __INLINE inline /*!< inline keyword for GNU Compiler */
81  #define __STATIC_INLINE static inline
82 
83 #elif defined ( __TASKING__ )
84  #define __ASM __asm /*!< asm keyword for TASKING Compiler */
85  #define __INLINE inline /*!< inline keyword for TASKING Compiler */
86  #define __STATIC_INLINE static inline
87 
88 #endif
89 
90 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
91 */
92 #define __FPU_USED 0
93 
94 #if defined ( __CC_ARM )
95  #if defined __TARGET_FPU_VFP
96  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
97  #endif
98 
99 #elif defined ( __ICCARM__ )
100  #if defined __ARMVFP__
101  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102  #endif
103 
104 #elif defined ( __TMS470__ )
105  #if defined __TI__VFP_SUPPORT____
106  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107  #endif
108 
109 #elif defined ( __GNUC__ )
110  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
111  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
112  #endif
113 
114 #elif defined ( __TASKING__ )
115  #if defined __FPU_VFP__
116  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
117  #endif
118 #endif
119 
120 #include <stdint.h> /* standard types definitions */
121 #include <core_cmInstr.h> /* Core Instruction Access */
122 #include <core_cmFunc.h> /* Core Function Access */
123 
124 #endif /* __CORE_CM3_H_GENERIC */
125 
126 #ifndef __CMSIS_GENERIC
127 
128 #ifndef __CORE_CM3_H_DEPENDANT
129 #define __CORE_CM3_H_DEPENDANT
130 
131 /* check device defines and use defaults */
132 #if defined __CHECK_DEVICE_DEFINES
133  #ifndef __CM3_REV
134  #define __CM3_REV 0x0200
135  #warning "__CM3_REV not defined in device header file; using default!"
136  #endif
137 
138  #ifndef __MPU_PRESENT
139  #define __MPU_PRESENT 0
140  #warning "__MPU_PRESENT not defined in device header file; using default!"
141  #endif
142 
143  #ifndef __NVIC_PRIO_BITS
144  #define __NVIC_PRIO_BITS 4
145  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
146  #endif
147 
148  #ifndef __Vendor_SysTickConfig
149  #define __Vendor_SysTickConfig 0
150  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
151  #endif
152 #endif
153 
154 /* IO definitions (access restrictions to peripheral registers) */
155 /**
156  \defgroup CMSIS_glob_defs CMSIS Global Defines
157 
158  <strong>IO Type Qualifiers</strong> are used
159  \li to specify the access to peripheral variables.
160  \li for automatic generation of peripheral register debug information.
161 */
162 #ifdef __cplusplus
163  #define __I volatile /*!< Defines 'read only' permissions */
164 #else
165  #define __I volatile const /*!< Defines 'read only' permissions */
166 #endif
167 #define __O volatile /*!< Defines 'write only' permissions */
168 #define __IO volatile /*!< Defines 'read / write' permissions */
169 
170 /*@} end of group Cortex_M3 */
171 
172 
173 
174 /*******************************************************************************
175  * Register Abstraction
176  Core Register contain:
177  - Core Register
178  - Core NVIC Register
179  - Core SCB Register
180  - Core SysTick Register
181  - Core Debug Register
182  - Core MPU Register
183  ******************************************************************************/
184 /** \defgroup CMSIS_core_register Defines and Type Definitions
185  \brief Type definitions and defines for Cortex-M processor based devices.
186 */
187 
188 /** \ingroup CMSIS_core_register
189  \defgroup CMSIS_CORE Status and Control Registers
190  \brief Core Register type definitions.
191  @{
192  */
193 
194 /** \brief Union type to access the Application Program Status Register (APSR).
195  */
196 typedef union
197 {
198  struct
199  {
200 #if (__CORTEX_M != 0x04)
201  uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
202 #else
203  uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
204  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
205  uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
206 #endif
207  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
208  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
209  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
210  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
211  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
212  } b; /*!< Structure used for bit access */
213  uint32_t w; /*!< Type used for word access */
214 } APSR_Type;
215 
216 
217 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
218  */
219 typedef union
220 {
221  struct
222  {
223  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
224  uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
225  } b; /*!< Structure used for bit access */
226  uint32_t w; /*!< Type used for word access */
227 } IPSR_Type;
228 
229 
230 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
231  */
232 typedef union
233 {
234  struct
235  {
236  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
237 #if (__CORTEX_M != 0x04)
238  uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
239 #else
240  uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
241  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
242  uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
243 #endif
244  uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
245  uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
246  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
247  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
248  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
249  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
250  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
251  } b; /*!< Structure used for bit access */
252  uint32_t w; /*!< Type used for word access */
253 } xPSR_Type;
254 
255 
256 /** \brief Union type to access the Control Registers (CONTROL).
257  */
258 typedef union
259 {
260  struct
261  {
262  uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
263  uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
264  uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
265  uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
266  } b; /*!< Structure used for bit access */
267  uint32_t w; /*!< Type used for word access */
268 } CONTROL_Type;
269 
270 /*@} end of group CMSIS_CORE */
271 
272 
273 /** \ingroup CMSIS_core_register
274  \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
275  \brief Type definitions for the NVIC Registers
276  @{
277  */
278 
279 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
280  */
281 typedef struct
282 {
283  __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
284  uint32_t RESERVED0[24];
285  __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
286  uint32_t RSERVED1[24];
287  __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
288  uint32_t RESERVED2[24];
289  __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
290  uint32_t RESERVED3[24];
291  __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
292  uint32_t RESERVED4[56];
293  __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
294  uint32_t RESERVED5[644];
295  __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
296 } NVIC_Type;
297 
298 /* Software Triggered Interrupt Register Definitions */
299 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
300 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
301 
302 /*@} end of group CMSIS_NVIC */
303 
304 
305 /** \ingroup CMSIS_core_register
306  \defgroup CMSIS_SCB System Control Block (SCB)
307  \brief Type definitions for the System Control Block Registers
308  @{
309  */
310 
311 /** \brief Structure type to access the System Control Block (SCB).
312  */
313 typedef struct
314 {
315  __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
316  __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
317  __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
318  __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
319  __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
320  __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
321  __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
322  __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
323  __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
324  __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
325  __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
326  __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
327  __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
328  __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
329  __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
330  __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
331  __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
332  __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
333  __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
334  uint32_t RESERVED0[5];
335  __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
336 } SCB_Type;
337 
338 /* SCB CPUID Register Definitions */
339 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
340 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
341 
342 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
343 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
344 
345 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
346 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
347 
348 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
349 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
350 
351 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
352 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
353 
354 /* SCB Interrupt Control State Register Definitions */
355 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
356 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
357 
358 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
359 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
360 
361 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
362 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
363 
364 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
365 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
366 
367 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
368 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
369 
370 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
371 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
372 
373 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
374 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
375 
376 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
377 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
378 
379 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
380 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
381 
382 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
383 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
384 
385 /* SCB Vector Table Offset Register Definitions */
386 #if (__CM3_REV < 0x0201) /* core r2p1 */
387 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
388 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
389 
390 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
391 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
392 #else
393 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
394 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
395 #endif
396 
397 /* SCB Application Interrupt and Reset Control Register Definitions */
398 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
399 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
400 
401 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
402 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
403 
404 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
405 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
406 
407 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
408 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
409 
410 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
411 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
412 
413 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
414 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
415 
416 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
417 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
418 
419 /* SCB System Control Register Definitions */
420 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
422 
423 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
425 
426 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
428 
429 /* SCB Configuration Control Register Definitions */
430 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
432 
433 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
434 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
435 
436 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
437 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
438 
439 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
440 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
441 
442 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
443 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
444 
445 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
446 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
447 
448 /* SCB System Handler Control and State Register Definitions */
449 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
450 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
451 
452 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
453 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
454 
455 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
456 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
457 
458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
460 
461 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
462 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
463 
464 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
465 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
466 
467 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
468 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
469 
470 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
471 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
472 
473 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
474 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
475 
476 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
477 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
478 
479 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
480 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
481 
482 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
483 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
484 
485 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
486 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
487 
488 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
489 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
490 
491 /* SCB Configurable Fault Status Registers Definitions */
492 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
493 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
494 
495 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
496 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
497 
498 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
499 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
500 
501 /* SCB Hard Fault Status Registers Definitions */
502 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
503 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
504 
505 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
506 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
507 
508 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
509 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
510 
511 /* SCB Debug Fault Status Register Definitions */
512 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
513 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
514 
515 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
516 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
517 
518 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
519 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
520 
521 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
522 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
523 
524 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
525 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
526 
527 /*@} end of group CMSIS_SCB */
528 
529 
530 /** \ingroup CMSIS_core_register
531  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
532  \brief Type definitions for the System Control and ID Register not in the SCB
533  @{
534  */
535 
536 /** \brief Structure type to access the System Control and ID Register not in the SCB.
537  */
538 typedef struct
539 {
540  uint32_t RESERVED0[1];
541  __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
542 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
543  __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
544 #else
545  uint32_t RESERVED1[1];
546 #endif
547 } SCnSCB_Type;
548 
549 /* Interrupt Controller Type Register Definitions */
550 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
551 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
552 
553 /* Auxiliary Control Register Definitions */
554 
555 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
556 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
557 
558 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
559 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
560 
561 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
562 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
563 
564 /*@} end of group CMSIS_SCnotSCB */
565 
566 
567 /** \ingroup CMSIS_core_register
568  \defgroup CMSIS_SysTick System Tick Timer (SysTick)
569  \brief Type definitions for the System Timer Registers.
570  @{
571  */
572 
573 /** \brief Structure type to access the System Timer (SysTick).
574  */
575 typedef struct
576 {
577  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
578  __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
579  __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
580  __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
581 } SysTick_Type;
582 
583 /* SysTick Control / Status Register Definitions */
584 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
585 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
586 
587 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
588 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
589 
590 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
591 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
592 
593 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
594 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
595 
596 /* SysTick Reload Register Definitions */
597 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
598 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
599 
600 /* SysTick Current Register Definitions */
601 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
602 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
603 
604 /* SysTick Calibration Register Definitions */
605 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
606 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
607 
608 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
609 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
610 
611 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
612 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
613 
614 /*@} end of group CMSIS_SysTick */
615 
616 
617 /** \ingroup CMSIS_core_register
618  \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
619  \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
620  @{
621  */
622 
623 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
624  */
625 typedef struct
626 {
627  __O union
628  {
629  __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
630  __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
631  __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
632  } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
633  uint32_t RESERVED0[864];
634  __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
635  uint32_t RESERVED1[15];
636  __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
637  uint32_t RESERVED2[15];
638  __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
639  uint32_t RESERVED3[29];
640  __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
641  __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
642  __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
643  uint32_t RESERVED4[43];
644  __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
645  __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
646  uint32_t RESERVED5[6];
647  __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
648  __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
649  __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
650  __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
651  __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
652  __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
653  __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
654  __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
655  __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
656  __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
657  __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
658  __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
659 } ITM_Type;
660 
661 /* ITM Trace Privilege Register Definitions */
662 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
663 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
664 
665 /* ITM Trace Control Register Definitions */
666 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
667 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
668 
669 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
670 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
671 
672 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
673 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
674 
675 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
676 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
677 
678 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
679 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
680 
681 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
682 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
683 
684 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
685 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
686 
687 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
688 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
689 
690 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
691 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
692 
693 /* ITM Integration Write Register Definitions */
694 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
695 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
696 
697 /* ITM Integration Read Register Definitions */
698 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
699 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
700 
701 /* ITM Integration Mode Control Register Definitions */
702 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
703 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
704 
705 /* ITM Lock Status Register Definitions */
706 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
707 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
708 
709 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
710 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
711 
712 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
713 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
714 
715 /*@}*/ /* end of group CMSIS_ITM */
716 
717 
718 /** \ingroup CMSIS_core_register
719  \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
720  \brief Type definitions for the Data Watchpoint and Trace (DWT)
721  @{
722  */
723 
724 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
725  */
726 typedef struct
727 {
728  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
729  __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
730  __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
731  __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
732  __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
733  __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
734  __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
735  __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
736  __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
737  __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
738  __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
739  uint32_t RESERVED0[1];
740  __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
741  __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
742  __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
743  uint32_t RESERVED1[1];
744  __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
745  __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
746  __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
747  uint32_t RESERVED2[1];
748  __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
749  __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
750  __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
751 } DWT_Type;
752 
753 /* DWT Control Register Definitions */
754 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
755 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
756 
757 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
758 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
759 
760 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
761 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
762 
763 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
764 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
765 
766 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
767 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
768 
769 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
770 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
771 
772 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
773 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
774 
775 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
776 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
777 
778 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
779 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
780 
781 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
782 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
783 
784 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
785 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
786 
787 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
788 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
789 
790 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
791 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
792 
793 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
794 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
795 
796 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
797 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
798 
799 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
800 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
801 
802 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
803 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
804 
805 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
806 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
807 
808 /* DWT CPI Count Register Definitions */
809 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
810 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
811 
812 /* DWT Exception Overhead Count Register Definitions */
813 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
814 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
815 
816 /* DWT Sleep Count Register Definitions */
817 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
818 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
819 
820 /* DWT LSU Count Register Definitions */
821 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
822 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
823 
824 /* DWT Folded-instruction Count Register Definitions */
825 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
826 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
827 
828 /* DWT Comparator Mask Register Definitions */
829 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
830 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
831 
832 /* DWT Comparator Function Register Definitions */
833 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
834 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
835 
836 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
837 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
838 
839 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
840 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
841 
842 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
843 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
844 
845 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
846 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
847 
848 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
849 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
850 
851 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
852 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
853 
854 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
855 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
856 
857 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
858 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
859 
860 /*@}*/ /* end of group CMSIS_DWT */
861 
862 
863 /** \ingroup CMSIS_core_register
864  \defgroup CMSIS_TPI Trace Port Interface (TPI)
865  \brief Type definitions for the Trace Port Interface (TPI)
866  @{
867  */
868 
869 /** \brief Structure type to access the Trace Port Interface Register (TPI).
870  */
871 typedef struct
872 {
873  __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
874  __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
875  uint32_t RESERVED0[2];
876  __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
877  uint32_t RESERVED1[55];
878  __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
879  uint32_t RESERVED2[131];
880  __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
881  __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
882  __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
883  uint32_t RESERVED3[759];
884  __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
885  __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
886  __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
887  uint32_t RESERVED4[1];
888  __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
889  __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
890  __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
891  uint32_t RESERVED5[39];
892  __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
893  __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
894  uint32_t RESERVED7[8];
895  __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
896  __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
897 } TPI_Type;
898 
899 /* TPI Asynchronous Clock Prescaler Register Definitions */
900 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
901 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
902 
903 /* TPI Selected Pin Protocol Register Definitions */
904 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
905 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
906 
907 /* TPI Formatter and Flush Status Register Definitions */
908 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
909 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
910 
911 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
912 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
913 
914 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
915 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
916 
917 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
918 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
919 
920 /* TPI Formatter and Flush Control Register Definitions */
921 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
922 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
923 
924 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
925 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
926 
927 /* TPI TRIGGER Register Definitions */
928 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
929 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
930 
931 /* TPI Integration ETM Data Register Definitions (FIFO0) */
932 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
933 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
934 
935 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
936 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
937 
938 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
939 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
940 
941 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
942 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
943 
944 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
945 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
946 
947 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
948 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
949 
950 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
951 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
952 
953 /* TPI ITATBCTR2 Register Definitions */
954 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
955 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
956 
957 /* TPI Integration ITM Data Register Definitions (FIFO1) */
958 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
959 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
960 
961 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
962 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
963 
964 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
965 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
966 
967 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
968 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
969 
970 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
971 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
972 
973 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
974 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
975 
976 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
977 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
978 
979 /* TPI ITATBCTR0 Register Definitions */
980 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
981 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
982 
983 /* TPI Integration Mode Control Register Definitions */
984 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
985 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
986 
987 /* TPI DEVID Register Definitions */
988 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
989 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
990 
991 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
992 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
993 
994 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
995 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
996 
997 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
998 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
999 
1000 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1001 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1002 
1003 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1004 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
1005 
1006 /* TPI DEVTYPE Register Definitions */
1007 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1008 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
1009 
1010 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1011 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1012 
1013 /*@}*/ /* end of group CMSIS_TPI */
1014 
1015 
1016 #if (__MPU_PRESENT == 1)
1017 /** \ingroup CMSIS_core_register
1018  \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1019  \brief Type definitions for the Memory Protection Unit (MPU)
1020  @{
1021  */
1022 
1023 /** \brief Structure type to access the Memory Protection Unit (MPU).
1024  */
1025 typedef struct
1026 {
1027  __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1028  __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1029  __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1030  __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1031  __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1032  __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1033  __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1034  __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1035  __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1036  __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1037  __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1038 } MPU_Type;
1039 
1040 /* MPU Type Register */
1041 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1042 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1043 
1044 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1045 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1046 
1047 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1048 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1049 
1050 /* MPU Control Register */
1051 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1052 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1053 
1054 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1055 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1056 
1057 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1058 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1059 
1060 /* MPU Region Number Register */
1061 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1062 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1063 
1064 /* MPU Region Base Address Register */
1065 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1066 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1067 
1068 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1069 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1070 
1071 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1072 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1073 
1074 /* MPU Region Attribute and Size Register */
1075 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1076 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1077 
1078 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1079 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1080 
1081 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1082 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1083 
1084 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1085 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1086 
1087 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1088 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1089 
1090 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1091 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1092 
1093 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1094 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1095 
1096 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1097 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1098 
1099 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1100 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1101 
1102 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1103 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1104 
1105 /*@} end of group CMSIS_MPU */
1106 #endif
1107 
1108 
1109 /** \ingroup CMSIS_core_register
1110  \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1111  \brief Type definitions for the Core Debug Registers
1112  @{
1113  */
1114 
1115 /** \brief Structure type to access the Core Debug Register (CoreDebug).
1116  */
1117 typedef struct
1118 {
1119  __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1120  __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1121  __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1122  __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1123 } CoreDebug_Type;
1124 
1125 /* Debug Halting Control and Status Register */
1126 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1127 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1128 
1129 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1130 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1131 
1132 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1133 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1134 
1135 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1136 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1137 
1138 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1139 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1140 
1141 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1142 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1143 
1144 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1145 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1146 
1147 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1148 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1149 
1150 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1151 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1152 
1153 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1154 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1155 
1156 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1157 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1158 
1159 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1160 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1161 
1162 /* Debug Core Register Selector Register */
1163 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1164 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1165 
1166 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1167 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1168 
1169 /* Debug Exception and Monitor Control Register */
1170 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1171 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1172 
1173 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1174 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1175 
1176 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1177 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1178 
1179 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1180 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1181 
1182 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1183 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1184 
1185 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1186 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1187 
1188 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1189 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1190 
1191 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1192 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1193 
1194 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1195 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1196 
1197 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1198 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1199 
1200 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1201 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1202 
1203 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1204 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1205 
1206 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1207 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1208 
1209 /*@} end of group CMSIS_CoreDebug */
1210 
1211 
1212 /** \ingroup CMSIS_core_register
1213  \defgroup CMSIS_core_base Core Definitions
1214  \brief Definitions for base addresses, unions, and structures.
1215  @{
1216  */
1217 
1218 /* Memory mapping of Cortex-M3 Hardware */
1219 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1220 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1221 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1222 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1223 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1224 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1225 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1226 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1227 
1228 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1229 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1230 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1231 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1232 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1233 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1234 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1235 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1236 
1237 #if (__MPU_PRESENT == 1)
1238  #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1239  #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1240 #endif
1241 
1242 /*@} */
1243 
1244 
1245 
1246 /*******************************************************************************
1247  * Hardware Abstraction Layer
1248  Core Function Interface contains:
1249  - Core NVIC Functions
1250  - Core SysTick Functions
1251  - Core Debug Functions
1252  - Core Register Access Functions
1253  ******************************************************************************/
1254 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1255 */
1256 
1257 
1258 
1259 /* ########################## NVIC functions #################################### */
1260 /** \ingroup CMSIS_Core_FunctionInterface
1261  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1262  \brief Functions that manage interrupts and exceptions via the NVIC.
1263  @{
1264  */
1265 
1266 /** \brief Set Priority Grouping
1267 
1268  The function sets the priority grouping field using the required unlock sequence.
1269  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1270  Only values from 0..7 are used.
1271  In case of a conflict between priority grouping and available
1272  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1273 
1274  \param [in] PriorityGroup Priority grouping field.
1275  */
1276 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1277 {
1278  uint32_t reg_value;
1279  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1280 
1281  reg_value = SCB->AIRCR; /* read old register configuration */
1282  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1283  reg_value = (reg_value |
1284  ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1285  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1286  SCB->AIRCR = reg_value;
1287 }
1288 
1289 
1290 /** \brief Get Priority Grouping
1291 
1292  The function reads the priority grouping field from the NVIC Interrupt Controller.
1293 
1294  \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1295  */
1296 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1297 {
1298  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1299 }
1300 
1301 
1302 /** \brief Enable External Interrupt
1303 
1304  The function enables a device-specific interrupt in the NVIC interrupt controller.
1305 
1306  \param [in] IRQn External interrupt number. Value cannot be negative.
1307  */
1308 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1309 {
1310  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1311 }
1312 
1313 
1314 /** \brief Disable External Interrupt
1315 
1316  The function disables a device-specific interrupt in the NVIC interrupt controller.
1317 
1318  \param [in] IRQn External interrupt number. Value cannot be negative.
1319  */
1320 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1321 {
1322  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1323 }
1324 
1325 
1326 /** \brief Get Pending Interrupt
1327 
1328  The function reads the pending register in the NVIC and returns the pending bit
1329  for the specified interrupt.
1330 
1331  \param [in] IRQn Interrupt number.
1332 
1333  \return 0 Interrupt status is not pending.
1334  \return 1 Interrupt status is pending.
1335  */
1336 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1337 {
1338  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1339 }
1340 
1341 
1342 /** \brief Set Pending Interrupt
1343 
1344  The function sets the pending bit of an external interrupt.
1345 
1346  \param [in] IRQn Interrupt number. Value cannot be negative.
1347  */
1348 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1349 {
1350  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1351 }
1352 
1353 
1354 /** \brief Clear Pending Interrupt
1355 
1356  The function clears the pending bit of an external interrupt.
1357 
1358  \param [in] IRQn External interrupt number. Value cannot be negative.
1359  */
1360 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1361 {
1362  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1363 }
1364 
1365 
1366 /** \brief Get Active Interrupt
1367 
1368  The function reads the active register in NVIC and returns the active bit.
1369 
1370  \param [in] IRQn Interrupt number.
1371 
1372  \return 0 Interrupt status is not active.
1373  \return 1 Interrupt status is active.
1374  */
1375 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1376 {
1377  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1378 }
1379 
1380 
1381 /** \brief Set Interrupt Priority
1382 
1383  The function sets the priority of an interrupt.
1384 
1385  \note The priority cannot be set for every core interrupt.
1386 
1387  \param [in] IRQn Interrupt number.
1388  \param [in] priority Priority to set.
1389  */
1390 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1391 {
1392  if(IRQn < 0) {
1393  SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1394  else {
1395  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1396 }
1397 
1398 
1399 /** \brief Get Interrupt Priority
1400 
1401  The function reads the priority of an interrupt. The interrupt
1402  number can be positive to specify an external (device specific)
1403  interrupt, or negative to specify an internal (core) interrupt.
1404 
1405 
1406  \param [in] IRQn Interrupt number.
1407  \return Interrupt Priority. Value is aligned automatically to the implemented
1408  priority bits of the microcontroller.
1409  */
1410 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1411 {
1412 
1413  if(IRQn < 0) {
1414  return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1415  else {
1416  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1417 }
1418 
1419 
1420 /** \brief Encode Priority
1421 
1422  The function encodes the priority for an interrupt with the given priority group,
1423  preemptive priority value, and subpriority value.
1424  In case of a conflict between priority grouping and available
1425  priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
1426 
1427  \param [in] PriorityGroup Used priority group.
1428  \param [in] PreemptPriority Preemptive priority value (starting from 0).
1429  \param [in] SubPriority Subpriority value (starting from 0).
1430  \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1431  */
1432 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1433 {
1434  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1435  uint32_t PreemptPriorityBits;
1436  uint32_t SubPriorityBits;
1437 
1438  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1439  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1440 
1441  return (
1442  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1443  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1444  );
1445 }
1446 
1447 
1448 /** \brief Decode Priority
1449 
1450  The function decodes an interrupt priority value with a given priority group to
1451  preemptive priority value and subpriority value.
1452  In case of a conflict between priority grouping and available
1453  priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1454 
1455  \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1456  \param [in] PriorityGroup Used priority group.
1457  \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1458  \param [out] pSubPriority Subpriority value (starting from 0).
1459  */
1460 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1461 {
1462  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1463  uint32_t PreemptPriorityBits;
1464  uint32_t SubPriorityBits;
1465 
1466  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1467  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1468 
1469  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1470  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1471 }
1472 
1473 
1474 /** \brief System Reset
1475 
1476  The function initiates a system reset request to reset the MCU.
1477  */
1478 __STATIC_INLINE void NVIC_SystemReset(void)
1479 {
1480  __DSB(); /* Ensure all outstanding memory accesses included
1481  buffered write are completed before reset */
1482  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1483  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1484  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1485  __DSB(); /* Ensure completion of memory access */
1486  while(1); /* wait until reset */
1487 }
1488 
1489 /*@} end of CMSIS_Core_NVICFunctions */
1490 
1491 
1492 
1493 /* ################################## SysTick function ############################################ */
1494 /** \ingroup CMSIS_Core_FunctionInterface
1495  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1496  \brief Functions that configure the System.
1497  @{
1498  */
1499 
1500 #if (__Vendor_SysTickConfig == 0)
1501 
1502 /** \brief System Tick Configuration
1503 
1504  The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1505  Counter is in free running mode to generate periodic interrupts.
1506 
1507  \param [in] ticks Number of ticks between two interrupts.
1508 
1509  \return 0 Function succeeded.
1510  \return 1 Function failed.
1511 
1512  \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1513  function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1514  must contain a vendor-specific implementation of this function.
1515 
1516  */
1517 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1518 {
1519  if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1520 
1521  SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1522  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1523  SysTick->VAL = 0; /* Load the SysTick Counter Value */
1524  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1525  SysTick_CTRL_TICKINT_Msk |
1526  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1527  return (0); /* Function successful */
1528 }
1529 
1530 #endif
1531 
1532 /*@} end of CMSIS_Core_SysTickFunctions */
1533 
1534 
1535 
1536 /* ##################################### Debug In/Output function ########################################### */
1537 /** \ingroup CMSIS_Core_FunctionInterface
1538  \defgroup CMSIS_core_DebugFunctions ITM Functions
1539  \brief Functions that access the ITM debug interface.
1540  @{
1541  */
1542 
1543 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1544 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1545 
1546 
1547 /** \brief ITM Send Character
1548 
1549  The function transmits a character via the ITM channel 0, and
1550  \li Just returns when no debugger is connected that has booked the output.
1551  \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1552 
1553  \param [in] ch Character to transmit.
1554 
1555  \returns Character to transmit.
1556  */
1557 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1558 {
1559  if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1560  (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1561  {
1562  while (ITM->PORT[0].u32 == 0);
1563  ITM->PORT[0].u8 = (uint8_t) ch;
1564  }
1565  return (ch);
1566 }
1567 
1568 
1569 /** \brief ITM Receive Character
1570 
1571  The function inputs a character via the external variable \ref ITM_RxBuffer.
1572 
1573  \return Received character.
1574  \return -1 No character pending.
1575  */
1576 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1577  int32_t ch = -1; /* no character available */
1578 
1579  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1580  ch = ITM_RxBuffer;
1581  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1582  }
1583 
1584  return (ch);
1585 }
1586 
1587 
1588 /** \brief ITM Check Character
1589 
1590  The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1591 
1592  \return 0 No character available.
1593  \return 1 Character available.
1594  */
1595 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1596 
1597  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1598  return (0); /* no character available */
1599  } else {
1600  return (1); /* character available */
1601  }
1602 }
1603 
1604 /*@} end of CMSIS_core_DebugFunctions */
1605 
1606 #endif /* __CORE_CM3_H_DEPENDANT */
1607 
1608 #endif /* __CMSIS_GENERIC */
1609 
1610 #ifdef __cplusplus
1611 }
1612 #endif