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ARMCM0plus.h
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1 /**************************************************************************//**
2  * @file ARMCM0plus.h
3  * @brief CMSIS Core Peripheral Access Layer Header File for
4  * ARMCM0plus Device Series
5  * @version V1.00
6  * @date 19. March 2012
7  *
8  * @note
9  * Copyright (C) 2012 ARM Limited. All rights reserved.
10  *
11  * @par
12  * ARM Limited (ARM) is supplying this software for use with Cortex-M
13  * processor based microcontrollers. This file can be freely distributed
14  * within development tools that are supporting such ARM based processors.
15  *
16  * @par
17  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22  *
23  ******************************************************************************/
24 
25 #ifndef ARMCM0plus_H
26 #define ARMCM0plus_H
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 
33 /* ------------------------- Interrupt Number Definition ------------------------ */
34 
35 typedef enum IRQn
36 {
37 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
38  NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
39  HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
40 
41 
42 
43  SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
44 
45  PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
46  SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
47 
48 /* ---------------------- ARMCM0 Specific Interrupt Numbers --------------------- */
49  WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
50  RTC_IRQn = 1, /*!< Real Time Clock Interrupt */
51  TIM0_IRQn = 2, /*!< Timer0 / Timer1 Interrupt */
52  TIM2_IRQn = 3, /*!< Timer2 / Timer3 Interrupt */
53  MCIA_IRQn = 4, /*!< MCIa Interrupt */
54  MCIB_IRQn = 5, /*!< MCIb Interrupt */
55  UART0_IRQn = 6, /*!< UART0 Interrupt */
56  UART1_IRQn = 7, /*!< UART1 Interrupt */
57  UART2_IRQn = 8, /*!< UART2 Interrupt */
58  UART4_IRQn = 9, /*!< UART4 Interrupt */
59  AACI_IRQn = 10, /*!< AACI / AC97 Interrupt */
60  CLCD_IRQn = 11, /*!< CLCD Combined Interrupt */
61  ENET_IRQn = 12, /*!< Ethernet Interrupt */
62  USBDC_IRQn = 13, /*!< USB Device Interrupt */
63  USBHC_IRQn = 14, /*!< USB Host Controller Interrupt */
64  CHLCD_IRQn = 15, /*!< Character LCD Interrupt */
65  FLEXRAY_IRQn = 16, /*!< Flexray Interrupt */
66  CAN_IRQn = 17, /*!< CAN Interrupt */
67  LIN_IRQn = 18, /*!< LIN Interrupt */
68  I2C_IRQn = 19, /*!< I2C ADC/DAC Interrupt */
69  CPU_CLCD_IRQn = 28, /*!< CPU CLCD Combined Interrupt */
70  UART3_IRQn = 30, /*!< UART3 Interrupt */
71  SPI_IRQn = 31, /*!< SPI Touchscreen Interrupt */
72 } IRQn_Type;
73 
74 
75 /* ================================================================================ */
76 /* ================ Processor and Core Peripheral Section ================ */
77 /* ================================================================================ */
78 
79 /* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
80 #define __CM0PLUS_REV 0x0000 /*!< Core revision r0p0 */
81 #define __MPU_PRESENT 0 /*!< MPU present or not */
82 #define __VTOR_PRESENT 0 /*!< VTOR present or not */
83 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
84 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
85 
86 #include <core_cm0plus.h> /* Processor and core peripherals */
87 #include "system_ARMCM0plus.h" /* System Header */
88 
89 
90 /* ================================================================================ */
91 /* ================ Device Specific Peripheral Section ================ */
92 /* ================================================================================ */
93 
94 /* ------------------- Start of section using anonymous unions ------------------ */
95 #if defined(__CC_ARM)
96  #pragma push
97  #pragma anon_unions
98 #elif defined(__ICCARM__)
99  #pragma language=extended
100 #elif defined(__GNUC__)
101  /* anonymous unions are enabled by default */
102 #elif defined(__TMS470__)
103 /* anonymous unions are enabled by default */
104 #elif defined(__TASKING__)
105  #pragma warning 586
106 #else
107  #warning Not supported compiler type
108 #endif
109 
110 
111 
112 /* ================================================================================ */
113 /* ================ CPU FPGA System (CPU_SYS) ================ */
114 /* ================================================================================ */
115 typedef struct
116 {
117  __I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
118  __IO uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
119  __I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
120  __IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
121  __I uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
122  __IO uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
123  uint32_t RESERVED0[2];
124  __IO uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
125  __IO uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
126  __IO uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
127  uint32_t RESERVED1[3];
128  __IO uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
129  __IO uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
130 } ARM_CPU_SYS_TypeDef;
131 
132 
133 /* ================================================================================ */
134 /* ================ DUT FPGA System (DUT_SYS) ================ */
135 /* ================================================================================ */
136 typedef struct
137 {
138  __I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
139  __IO uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
140  __I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
141  __IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
142  __IO uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
143  __I uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
144  __I uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
145 } ARM_DUT_SYS_TypeDef;
146 
147 
148 /* ================================================================================ */
149 /* ================ Timer (TIM) ================ */
150 /* ================================================================================ */
151 typedef struct
152 {
153  __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
154  __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
155  __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
156  __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
157  __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
158  __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
159  __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
160  uint32_t RESERVED0[1];
161  __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
162  __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
163  __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
164  __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
165  __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
166  __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
167  __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
168 } ARM_TIM_TypeDef;
169 
170 
171 /* ================================================================================ */
172 /* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
173 /* ================================================================================ */
174 typedef struct
175 {
176  __IO uint32_t DR; /* Offset: 0x000 (R/W) Data */
177  union {
178  __I uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
179  __O uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
180  };
181  uint32_t RESERVED0[4];
182  __IO uint32_t FR; /* Offset: 0x018 (R/W) Flags */
183  uint32_t RESERVED1[1];
184  __IO uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
185  __IO uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
186  __IO uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
187  __IO uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
188  __IO uint32_t CR; /* Offset: 0x030 (R/W) Control */
189  __IO uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
190  __IO uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
191  __IO uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
192  __IO uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
193  __O uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
194  __IO uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
195 } ARM_UART_TypeDef;
196 
197 
198 /* -------------------- End of section using anonymous unions ------------------- */
199 #if defined(__CC_ARM)
200  #pragma pop
201 #elif defined(__ICCARM__)
202  /* leave anonymous unions enabled */
203 #elif defined(__GNUC__)
204  /* anonymous unions are enabled by default */
205 #elif defined(__TMS470__)
206  /* anonymous unions are enabled by default */
207 #elif defined(__TASKING__)
208  #pragma warning restore
209 #else
210  #warning Not supported compiler type
211 #endif
212 
213 
214 
215 
216 /* ================================================================================ */
217 /* ================ Peripheral memory map ================ */
218 /* ================================================================================ */
219 /* -------------------------- CPU FPGA memory map ------------------------------- */
220 #define ARM_FLASH_BASE (0x00000000UL)
221 #define ARM_RAM_BASE (0x20000000UL)
222 #define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
223 #define ARM_CPU_CFG_BASE (0xDFFF0000UL)
224 
225 #define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000)
226 #define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000)
227 
228 /* -------------------------- DUT FPGA memory map ------------------------------- */
229 #define ARM_APB_BASE (0x40000000UL)
230 #define ARM_AHB_BASE (0x4FF00000UL)
231 #define ARM_DMC_BASE (0x60000000UL)
232 #define ARM_SMC_BASE (0xA0000000UL)
233 
234 #define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000)
235 #define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000)
236 #define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000)
237 #define ARM_UART0_BASE (ARM_APB_BASE + 0x06000)
238 #define ARM_UART1_BASE (ARM_APB_BASE + 0x07000)
239 #define ARM_UART2_BASE (ARM_APB_BASE + 0x08000)
240 #define ARM_UART4_BASE (ARM_APB_BASE + 0x09000)
241 
242 
243 /* ================================================================================ */
244 /* ================ Peripheral declaration ================ */
245 /* ================================================================================ */
246 /* -------------------------- CPU FPGA Peripherals ------------------------------ */
247 #define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
248 #define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
249 
250 /* -------------------------- DUT FPGA Peripherals ------------------------------ */
251 #define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
252 #define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
253 #define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
254 #define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
255 #define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
256 #define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
257 #define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
258 
259 
260 #ifdef __cplusplus
261 }
262 #endif
263 
264 #endif /* ARMCM0plus_H */