CMSIS2000  0.0.7
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startup_ARMSC000.s
См. документацию.
1 ;/**************************************************************************//**
2 ; * @file startup_ARMSC000.s
3 ; * @brief CMSIS Core Device Startup File for
4 ; * ARMSC000 Device Series
5 ; * @version V1.08
6 ; * @date 03. February 2012
7 ; *
8 ; * @note
9 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
10 ; *
11 ; * @par
12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
13 ; * processor based microcontrollers. This file can be freely distributed
14 ; * within development tools that are supporting such ARM based processors.
15 ; *
16 ; * @par
17 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22 ; *
23 ; ******************************************************************************/
24 ;/*
25 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
26 ;*/
27 
28 
29 ; <h> Stack Configuration
30 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
31 ; </h>
32 
33 Stack_Size EQU 0x00000400
34 
35  AREA STACK, NOINIT, READWRITE, ALIGN=3
36 Stack_Mem SPACE Stack_Size
37 __initial_sp
38 
39 
40 ; <h> Heap Configuration
41 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
42 ; </h>
43 
44 Heap_Size EQU 0x00000C00
45 
46  AREA HEAP, NOINIT, READWRITE, ALIGN=3
47 __heap_base
48 Heap_Mem SPACE Heap_Size
49 __heap_limit
50 
51 
52  PRESERVE8
53  THUMB
54 
55 
56 ; Vector Table Mapped to Address 0 at Reset
57 
58  AREA RESET, DATA, READONLY
59  EXPORT __Vectors
60  EXPORT __Vectors_End
61  EXPORT __Vectors_Size
62 
63 __Vectors DCD __initial_sp ; Top of Stack
64  DCD Reset_Handler ; Reset Handler
65  DCD NMI_Handler ; NMI Handler
66  DCD HardFault_Handler ; Hard Fault Handler
67  DCD 0 ; Reserved
68  DCD 0 ; Reserved
69  DCD 0 ; Reserved
70  DCD 0 ; Reserved
71  DCD 0 ; Reserved
72  DCD 0 ; Reserved
73  DCD 0 ; Reserved
74  DCD SVC_Handler ; SVCall Handler
75  DCD 0 ; Reserved
76  DCD 0 ; Reserved
77  DCD PendSV_Handler ; PendSV Handler
78  DCD SysTick_Handler ; SysTick Handler
79 
80  ; External Interrupts
81  DCD WDT_IRQHandler ; 0: Watchdog Timer
82  DCD RTC_IRQHandler ; 1: Real Time Clock
83  DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
84  DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
85  DCD MCIA_IRQHandler ; 4: MCIa
86  DCD MCIB_IRQHandler ; 5: MCIb
87  DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
88  DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
89  DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
90  DCD UART4_IRQHandler ; 9: UART4 - not connected
91  DCD AACI_IRQHandler ; 10: AACI / AC97
92  DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
93  DCD ENET_IRQHandler ; 12: Ethernet
94  DCD USBDC_IRQHandler ; 13: USB Device
95  DCD USBHC_IRQHandler ; 14: USB Host Controller
96  DCD CHLCD_IRQHandler ; 15: Character LCD
97  DCD FLEXRAY_IRQHandler ; 16: Flexray
98  DCD CAN_IRQHandler ; 17: CAN
99  DCD LIN_IRQHandler ; 18: LIN
100  DCD I2C_IRQHandler ; 19: I2C ADC/DAC
101  DCD 0 ; 20: Reserved
102  DCD 0 ; 21: Reserved
103  DCD 0 ; 22: Reserved
104  DCD 0 ; 23: Reserved
105  DCD 0 ; 24: Reserved
106  DCD 0 ; 25: Reserved
107  DCD 0 ; 26: Reserved
108  DCD 0 ; 27: Reserved
109  DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
110  DCD 0 ; 29: Reserved - CPU FPGA
111  DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
112  DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
113 __Vectors_End
114 
115 __Vectors_Size EQU __Vectors_End - __Vectors
116 
117  AREA |.text|, CODE, READONLY
118 
119 
120 ; Reset Handler
121 
122 Reset_Handler PROC
123  EXPORT Reset_Handler [WEAK]
124  IMPORT SystemInit
125  IMPORT __main
126  LDR R0, =SystemInit
127  BLX R0
128  LDR R0, =__main
129  BX R0
130  ENDP
131 
132 
133 ; Dummy Exception Handlers (infinite loops which can be modified)
134 
135 NMI_Handler PROC
136  EXPORT NMI_Handler [WEAK]
137  B .
138  ENDP
139 HardFault_Handler\
140  PROC
141  EXPORT HardFault_Handler [WEAK]
142  B .
143  ENDP
144 SVC_Handler PROC
145  EXPORT SVC_Handler [WEAK]
146  B .
147  ENDP
148 PendSV_Handler PROC
149  EXPORT PendSV_Handler [WEAK]
150  B .
151  ENDP
152 SysTick_Handler PROC
153  EXPORT SysTick_Handler [WEAK]
154  B .
155  ENDP
156 
157 Default_Handler PROC
158 
159  EXPORT WDT_IRQHandler [WEAK]
160  EXPORT RTC_IRQHandler [WEAK]
161  EXPORT TIM0_IRQHandler [WEAK]
162  EXPORT TIM2_IRQHandler [WEAK]
163  EXPORT MCIA_IRQHandler [WEAK]
164  EXPORT MCIB_IRQHandler [WEAK]
165  EXPORT UART0_IRQHandler [WEAK]
166  EXPORT UART1_IRQHandler [WEAK]
167  EXPORT UART2_IRQHandler [WEAK]
168  EXPORT UART3_IRQHandler [WEAK]
169  EXPORT UART4_IRQHandler [WEAK]
170  EXPORT AACI_IRQHandler [WEAK]
171  EXPORT CLCD_IRQHandler [WEAK]
172  EXPORT ENET_IRQHandler [WEAK]
173  EXPORT USBDC_IRQHandler [WEAK]
174  EXPORT USBHC_IRQHandler [WEAK]
175  EXPORT CHLCD_IRQHandler [WEAK]
176  EXPORT FLEXRAY_IRQHandler [WEAK]
177  EXPORT CAN_IRQHandler [WEAK]
178  EXPORT LIN_IRQHandler [WEAK]
179  EXPORT I2C_IRQHandler [WEAK]
180  EXPORT CPU_CLCD_IRQHandler [WEAK]
181  EXPORT SPI_IRQHandler [WEAK]
182 
183 WDT_IRQHandler
184 RTC_IRQHandler
185 TIM0_IRQHandler
186 TIM2_IRQHandler
187 MCIA_IRQHandler
188 MCIB_IRQHandler
189 UART0_IRQHandler
190 UART1_IRQHandler
191 UART2_IRQHandler
192 UART3_IRQHandler
193 UART4_IRQHandler
194 AACI_IRQHandler
195 CLCD_IRQHandler
196 ENET_IRQHandler
197 USBDC_IRQHandler
198 USBHC_IRQHandler
199 CHLCD_IRQHandler
200 FLEXRAY_IRQHandler
201 CAN_IRQHandler
202 LIN_IRQHandler
203 I2C_IRQHandler
204 CPU_CLCD_IRQHandler
205 SPI_IRQHandler
206  B .
207 
208  ENDP
209 
210 
211  ALIGN
212 
213 
214 ; User Initial Stack & Heap
215 
216  IF :DEF:__MICROLIB
217 
218  EXPORT __initial_sp
219  EXPORT __heap_base
220  EXPORT __heap_limit
221 
222  ELSE
223 
224  IMPORT __use_two_region_memory
225  EXPORT __user_initial_stackheap
226 
227 __user_initial_stackheap PROC
228  LDR R0, = Heap_Mem
229  LDR R1, =(Stack_Mem + Stack_Size)
230  LDR R2, = (Heap_Mem + Heap_Size)
231  LDR R3, = Stack_Mem
232  BX LR
233  ENDP
234 
235  ALIGN
236 
237  ENDIF
238 
239 
240  END