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startup_ARMSC300.S
См. документацию.
1 /* File: startup_ARMSC300.S
2  * Purpose: startup file for SC300 devices. Should use with
3  * GCC for ARM Embedded Processors
4  * Version: V1.3
5  * Date: 08 Feb 2012
6  *
7  * Copyright (c) 2012, ARM Limited
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions are met:
12  * Redistributions of source code must retain the above copyright
13  notice, this list of conditions and the following disclaimer.
14  * Redistributions in binary form must reproduce the above copyright
15  notice, this list of conditions and the following disclaimer in the
16  documentation and/or other materials provided with the distribution.
17  * Neither the name of the ARM Limited nor the
18  names of its contributors may be used to endorse or promote products
19  derived from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24  * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32  .syntax unified
33  .arch armv7-m
34 
35  .section .stack
36  .align 3
37 #ifdef __STACK_SIZE
38  .equ Stack_Size, __STACK_SIZE
39 #else
40  .equ Stack_Size, 0x400
41 #endif
42  .globl __StackTop
43  .globl __StackLimit
44 __StackLimit:
45  .space Stack_Size
46  .size __StackLimit, . - __StackLimit
47 __StackTop:
48  .size __StackTop, . - __StackTop
49 
50  .section .heap
51  .align 3
52 #ifdef __HEAP_SIZE
53  .equ Heap_Size, __HEAP_SIZE
54 #else
55  .equ Heap_Size, 0xC00
56 #endif
57  .globl __HeapBase
58  .globl __HeapLimit
59 __HeapBase:
60  .if Heap_Size
61  .space Heap_Size
62  .endif
63  .size __HeapBase, . - __HeapBase
64 __HeapLimit:
65  .size __HeapLimit, . - __HeapLimit
66 
67  .section .isr_vector
68  .align 2
69  .globl __isr_vector
70 __isr_vector:
71  .long __StackTop /* Top of Stack */
72  .long Reset_Handler /* Reset Handler */
73  .long NMI_Handler /* NMI Handler */
74  .long HardFault_Handler /* Hard Fault Handler */
75  .long MemManage_Handler /* MPU Fault Handler */
76  .long BusFault_Handler /* Bus Fault Handler */
77  .long UsageFault_Handler /* Usage Fault Handler */
78  .long 0 /* Reserved */
79  .long 0 /* Reserved */
80  .long 0 /* Reserved */
81  .long 0 /* Reserved */
82  .long SVC_Handler /* SVCall Handler */
83  .long DebugMon_Handler /* Debug Monitor Handler */
84  .long 0 /* Reserved */
85  .long PendSV_Handler /* PendSV Handler */
86  .long SysTick_Handler /* SysTick Handler */
87 
88  /* External interrupts */
89  .long WDT_IRQHandler /* 0: Watchdog Timer */
90  .long RTC_IRQHandler /* 1: Real Time Clock */
91  .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
92  .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
93  .long MCIA_IRQHandler /* 4: MCIa */
94  .long MCIB_IRQHandler /* 5: MCIb */
95  .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
96  .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
97  .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
98  .long UART4_IRQHandler /* 9: UART4 - not connected */
99  .long AACI_IRQHandler /* 10: AACI / AC97 */
100  .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
101  .long ENET_IRQHandler /* 12: Ethernet */
102  .long USBDC_IRQHandler /* 13: USB Device */
103  .long USBHC_IRQHandler /* 14: USB Host Controller */
104  .long CHLCD_IRQHandler /* 15: Character LCD */
105  .long FLEXRAY_IRQHandler /* 16: Flexray */
106  .long CAN_IRQHandler /* 17: CAN */
107  .long LIN_IRQHandler /* 18: LIN */
108  .long I2C_IRQHandler /* 19: I2C ADC/DAC */
109  .long 0 /* 20: Reserved */
110  .long 0 /* 21: Reserved */
111  .long 0 /* 22: Reserved */
112  .long 0 /* 23: Reserved */
113  .long 0 /* 24: Reserved */
114  .long 0 /* 25: Reserved */
115  .long 0 /* 26: Reserved */
116  .long 0 /* 27: Reserved */
117  .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
118  .long 0 /* 29: Reserved - CPU FPGA */
119  .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
120  .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
121 
122  .size __isr_vector, . - __isr_vector
123 
124  .text
125  .thumb
126  .thumb_func
127  .align 2
128  .globl Reset_Handler
129  .type Reset_Handler, %function
130 Reset_Handler:
131 /* Loop to copy data from read only memory to RAM. The ranges
132  * of copy from/to are specified by following symbols evaluated in
133  * linker script.
134  * __etext: End of code section, i.e., begin of data sections to copy from.
135  * __data_start__/__data_end__: RAM address range that data should be
136  * copied to. Both must be aligned to 4 bytes boundary. */
137 
138  ldr r1, =__etext
139  ldr r2, =__data_start__
140  ldr r3, =__data_end__
141 
142 #if 1
143 /* Here are two copies of loop implemenations. First one favors code size
144  * and the second one favors performance. Default uses the first one.
145  * Change to "#if 0" to use the second one */
146 .flash_to_ram_loop:
147  cmp r2, r3
148  ittt lt
149  ldrlt r0, [r1], #4
150  strlt r0, [r2], #4
151  blt .flash_to_ram_loop
152 #else
153  subs r3, r2
154  ble .flash_to_ram_loop_end
155 .flash_to_ram_loop:
156  subs r3, #4
157  ldr r0, [r1, r3]
158  str r0, [r2, r3]
159  bgt .flash_to_ram_loop
160 .flash_to_ram_loop_end:
161 #endif
162 
163 #ifndef __NO_SYSTEM_INIT
164  ldr r0, =SystemInit
165  blx r0
166 #endif
167 
168  ldr r0, =_start
169  bx r0
170  .pool
171  .size Reset_Handler, . - Reset_Handler
172 
173 /* Macro to define default handlers. Default handler
174  * will be weak symbol and just dead loops. They can be
175  * overwritten by other handlers */
176  .macro def_irq_handler handler_name
177  .align 1
178  .thumb_func
179  .weak \handler_name
180  .type \handler_name, %function
181 \handler_name :
182  b .
183  .size \handler_name, . - \handler_name
184  .endm
185 
186  def_irq_handler NMI_Handler
187  def_irq_handler HardFault_Handler
188  def_irq_handler MemManage_Handler
189  def_irq_handler BusFault_Handler
190  def_irq_handler UsageFault_Handler
191  def_irq_handler SVC_Handler
192  def_irq_handler DebugMon_Handler
193  def_irq_handler PendSV_Handler
194  def_irq_handler SysTick_Handler
195  def_irq_handler Default_Handler
196 
197  def_irq_handler WDT_IRQHandler
198  def_irq_handler RTC_IRQHandler
199  def_irq_handler TIM0_IRQHandler
200  def_irq_handler TIM2_IRQHandler
201  def_irq_handler MCIA_IRQHandler
202  def_irq_handler MCIB_IRQHandler
203  def_irq_handler UART0_IRQHandler
204  def_irq_handler UART1_IRQHandler
205  def_irq_handler UART2_IRQHandler
206  def_irq_handler UART3_IRQHandler
207  def_irq_handler UART4_IRQHandler
208  def_irq_handler AACI_IRQHandler
209  def_irq_handler CLCD_IRQHandler
210  def_irq_handler ENET_IRQHandler
211  def_irq_handler USBDC_IRQHandler
212  def_irq_handler USBHC_IRQHandler
213  def_irq_handler CHLCD_IRQHandler
214  def_irq_handler FLEXRAY_IRQHandler
215  def_irq_handler CAN_IRQHandler
216  def_irq_handler LIN_IRQHandler
217  def_irq_handler I2C_IRQHandler
218  def_irq_handler CPU_CLCD_IRQHandler
219  def_irq_handler SPI_IRQHandler
220 
221  .end