lpc2xxx_old.h

См. документацию.

/*
 *  CMSIS2000
 *  CMSIS-like sources for LPC2xxx series MCUs
 *
 *  (C) Copyright 2011-2012, Dmitriy Cherepanov, All Rights Reserved
 *
 *  Version: 0.0.7
 *  Date of the Last Update:  2013-03-04
 *  
 *  Permission is hereby granted, free of charge, to any person obtaining a copy
 *  of this software and associated documentation files (the "Software"), to
 *  deal in the Software without restriction, including without limitation the
 *  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
 *  sell copies of the Software, and to permit persons to whom the Software is
 *  furnished to do so, subject to the following conditions:
 *
 *  The above copyright notice and this permission notice shall be included in
 *  all copies or substantial portions of the Software.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 *  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 *  IN THE SOFTWARE.
 *
 *  Do not be lasy! For the latest version see http://irtos.sourceforge.net .
 *
 *  
#*/

#ifndef _ARCH_ARM_NXP_LPC2XXX_H_
#define _ARCH_ARM_NXP_LPC2XXX_H_ 1
/*-----------Документация Doxygen  --  Doxygen documentation -----------------*/
/** \file
 *\~russian
 *      Адреса перефирийных регистров в LPC
 *\~english
 *      APB(ARM Peripheral Bus) peripheries registers addresses
 *\~
 *      \author Dmitriy Cherepanov
 *      \date 2010
 * \ingroup xgportARM7_NXP
 *\~russian
 *      \addtogroup xgportARM7_NXP Старый исходный код от NXP
 *\~english
 *      \addtogroup xgportARM7_NXP OLD Sources from NXP
 *\~

 *  @{
 */
/** \ingroup    xgportARM7_NXP
 *\if russian_lng
 *      \defgroup reg_addresses_LPC2000_old Адреса перефирийных регистров в LPC
 *\else
 *      \defgroup reg_addresses_LPC2000_old APB(ARM Peripheral Bus) peripheries registers addresses
 *\endif
 * \addtogroup reg_addresses_LPC2000_old
 *  @{
 */
#include "reg_macros.h"
#include "nxp_base_addresses.h"
/*-------------MCU NUMBER   --------------------------------------------------*/
/*if MCU has suffix 01 (for ex 2106/01) then is has new VIC and may be other modules */
#ifndef i_MCU_MODEL
        #define i_MCU_MODEL 0
#endif
/*------ МАКРОСЫ И ОПРЕДЕЛЕНИЯ - MACROSES ------------------------------------*/
// Vectored Interrupt Controller Registers (VIC)
#if i_MCU_MODEL >= 2300
        #define VIC_SIZE 32
typedef struct
{
  REG32 irqStatus;                      /**< IRQ Status Register                */
  REG32 fiqStatus;                      /**< FIQ Status Register                */
  REG32 rawIntr;                        /**< Raw Interrupt Status Register      */
  REG32 intSelect;                      /**< Interrupt Select Register          */
  REG32 intEnable;                      /**< Interrupt Enable Register          */
  REG32 intEnClr;                       /**< Interrupt Enable Clear Register    */
  REG32 softInt;                        /**< Software Interrupt Register        */
  REG32 softIntClear;                   /**< Software Interrupt Clear Register  */
  REG32 protection;                     /**< Protection Enable Register         */
  REG32 swPrioMask;                     /**< Software Priority Mask Register    */
  REG32 _pad0[4];
  REG32 _pad1[50];
  REG32 vectAddr[VIC_SIZE];             /**< Vector Address Registers           */
  REG32 _pad2[64-VIC_SIZE];
  REG32 vectCntl[VIC_SIZE];             /**< Vector Control Registers           */
  REG32 _pad3[800];
  REG32 address;                        /**< Vector Address Register            */
} vicRegs_t;
#else
        #define VIC_SIZE 16
typedef struct
{
  REG32 irqStatus;                      /**< IRQ Status Register                */
  REG32 fiqStatus;                      /**< FIQ Status Register                */
  REG32 rawIntr;                        /**< Raw Interrupt Status Register      */
  REG32 intSelect;                      /**< Interrupt Select Register          */
  REG32 intEnable;                      /**< Interrupt Enable Register          */
  REG32 intEnClr;                       /**< Interrupt Enable Clear Register    */
  REG32 softInt;                        /**< Software Interrupt Register        */
  REG32 softIntClr;                     /**< Software Interrupt Clear Register  */
  REG32 protection;                     /**< Protection Enable Register         */
  REG32 _pad0[3];
  REG32 address;                        /**< Vector Address Register            */
  REG32 defVectAddr;                    /**< Default Vector Address Register    */
  REG32 _pad1[50];

  REG32 vectAddr[VIC_SIZE];             /**< Vector Address Registers           */
  REG32 _pad2[64-VIC_SIZE];
  REG32 vectCntl[VIC_SIZE];             /**< Vector Control Registers           */
} vicRegs_t;
#endif

#define VIC_MAX_IRQ_NUMBER      (VIC_SIZE-1)

#define VIC_HIGHEST_PRIORITY    0x01
#define VIC_HIGH_PRIORITY       0x04
#define VIC_MEDIUM_PRIORITY     0x07
#define VIC_LOW_PRIORITY        0x0B
#define VIC_LOWEST_PRIORITY     0x0F


// Vectored Interrupt Controller
#define VIC                             ((vicRegs_t *)VIC_BASE)

#define IRQn_Type char

// VIC Channel Assignments
#define VIC_WDT         0
#define VIC_ARM_PROGRAMM_INT    2
#define VIC_ARM_CORE_ICE_RX     2
#define VIC_ARM_CORE_ICE_TX     3
#define VIC_TIMER0      4
#define VIC_TIMER1      5
#define VIC_UART0       6
#define VIC_UART1       7
#define VIC_PWM         8
#define VIC_PWM0        8
#define VIC_I2C         9
#define VIC_SPI         10
#define VIC_SPI0        10
#define VIC_SSP0        10
#define VIC_SPI1        11
#define VIC_SSP1        11
#define VIC_PLL         12
#define VIC_RTC         13
#define VIC_EINT0       14
#define VIC_EINT1       15
#define VIC_EINT2       16
#define VIC_EINT3       17
#define VIC_ADC         18
#if i_MCU_MODEL >= 2300
        #define VIC_I2C1                19
        #define VIC_BOD                 20
        #define VIC_EMAC                21
        #define VIC_USB                 22
        #define VIC_CAN                 23
        #define VIC_MCI                 24
        #define VIC_DMA                 25
        /* for lpc 24xx*/
        #define VIC_TIMER2              26
        #define VIC_TIMER3              27
        #define VIC_UART2               28
        #define VIC_UART3               29
        #define VIC_I2C2                30
        #define VIC_I2S                 31
#else
        #define VIC_CAN1_TX             20
        #define VIC_CAN2_TX             21
        #define VIC_CAN3_TX             22
        #define VIC_CAN4_TX             23
        #define VIC_RESERVE_23          24
        #define VIC_RESERVE_24          25
        #define VIC_CAN1_RX             26
        #define VIC_CAN2_RX             27
        #define VIC_CAN3_RX             28
        #define VIC_CAN4_RX             29
#endif





// Vector Control Register bit definitions
/// Vector Control Register -- Vector Interrupt Controller Enable
#define VIC_ENABLE      (1 << 5)

/// Vector Control Register -- Convert Channel Number to Bit Value
#define VIC_BIT(chan)   (1 << (chan))

#define VICIRQStatus    (*(REG32*)(VIC_BASE + 0x000))
#define VICFIQStatus    (*(REG32*)(VIC_BASE + 0x004))
#define VICRawIntr      (*(REG32*)(VIC_BASE + 0x008))
#define VICIntSelect    (*(REG32*)(VIC_BASE + 0x00C))
#define VICIntEnable    (*(REG32*)(VIC_BASE + 0x010))
#define VICIntEnClr     (*(REG32*)(VIC_BASE + 0x014))
#define VICSoftInt      (*(REG32*)(VIC_BASE + 0x018))
#define VICSoftIntClr   (*(REG32*)(VIC_BASE + 0x01C))
#define VICProtection   (*(REG32*)(VIC_BASE + 0x020))
#define VICSWPrioMask   (*(REG32*)(VIC_BASE + 0x024))

#define VICVectAddr     (*(REG32*)(VIC_BASE + 0xF00))

#define VICVectAddr_n(n)        (*(REG32*)(VIC_BASE + 256 + n*4))
#define VICVectAddr0    VICVectAddr_n(0)
#define VICVectAddr1    VICVectAddr_n(1)
#define VICVectAddr2    VICVectAddr_n(2)
#define VICVectAddr3    VICVectAddr_n(3)
#define VICVectAddr4    VICVectAddr_n(4)
#define VICVectAddr5    VICVectAddr_n(5)
#define VICVectAddr6    VICVectAddr_n(6)
#define VICVectAddr7    VICVectAddr_n(7)
#define VICVectAddr8    VICVectAddr_n(8)
#define VICVectAddr9    VICVectAddr_n(9)
#define VICVectAddr10   VICVectAddr_n(10)
#define VICVectAddr11   VICVectAddr_n(11)
#define VICVectAddr12   VICVectAddr_n(12)
#define VICVectAddr13   VICVectAddr_n(13)
#define VICVectAddr14   VICVectAddr_n(14)
#define VICVectAddr15   VICVectAddr_n(15)
#define VICVectAddr16   VICVectAddr_n(16)
#define VICVectAddr17   VICVectAddr_n(17)
#define VICVectAddr18   VICVectAddr_n(18)
#define VICVectAddr19   VICVectAddr_n(19)
#define VICVectAddr20   VICVectAddr_n(20)
#define VICVectAddr21   VICVectAddr_n(21)
#define VICVectAddr22   VICVectAddr_n(22)
#define VICVectAddr23   VICVectAddr_n(23)
#define VICVectAddr24   VICVectAddr_n(24)
#define VICVectAddr25   VICVectAddr_n(25)
#define VICVectAddr26   VICVectAddr_n(26)
#define VICVectAddr27   VICVectAddr_n(27)
#define VICVectAddr28   VICVectAddr_n(28)
#define VICVectAddr29   VICVectAddr_n(29)
#define VICVectAddr30   VICVectAddr_n(30)
#define VICVectAddr31   VICVectAddr_n(31)

#define VICVectCntl_n(n)        (*(REG32*)(VIC_BASE + 256*2 + n*4))
#define VICVectCntl0    VICVectCntl_n(0)
#define VICVectCntl1    VICVectCntl_n(1)
#define VICVectCntl2    VICVectCntl_n(2)
#define VICVectCntl3    VICVectCntl_n(3)
#define VICVectCntl4    VICVectCntl_n(4)
#define VICVectCntl5    VICVectCntl_n(5)
#define VICVectCntl6    VICVectCntl_n(6)
#define VICVectCntl7    VICVectCntl_n(7)
#define VICVectCntl8    VICVectCntl_n(8)
#define VICVectCntl9    VICVectCntl_n(9)
#define VICVectCntl10   VICVectCntl_n(10)
#define VICVectCntl11   VICVectCntl_n(11)
#define VICVectCntl12   VICVectCntl_n(12)
#define VICVectCntl13   VICVectCntl_n(13)
#define VICVectCntl14   VICVectCntl_n(14)
#define VICVectCntl15   VICVectCntl_n(15)
#define VICVectCntl16   VICVectCntl_n(16)
#define VICVectCntl17   VICVectCntl_n(17)
#define VICVectCntl18   VICVectCntl_n(18)
#define VICVectCntl19   VICVectCntl_n(19)
#define VICVectCntl20   VICVectCntl_n(20)
#define VICVectCntl21   VICVectCntl_n(21)
#define VICVectCntl22   VICVectCntl_n(22)
#define VICVectCntl23   VICVectCntl_n(23)
#define VICVectCntl24   VICVectCntl_n(24)
#define VICVectCntl25   VICVectCntl_n(25)
#define VICVectCntl26   VICVectCntl_n(26)
#define VICVectCntl27   VICVectCntl_n(27)
#define VICVectCntl28   VICVectCntl_n(28)
#define VICVectCntl29   VICVectCntl_n(29)
#define VICVectCntl30   VICVectCntl_n(30)
#define VICVectCntl31   VICVectCntl_n(31)
/*the same*/
#define VICVectPriority0        VICVectCntl_n(0)
#define VICVectPriority1        VICVectCntl_n(1)
#define VICVectPriority2        VICVectCntl_n(2)
#define VICVectPriority3        VICVectCntl_n(3)
#define VICVectPriority4        VICVectCntl_n(4)
#define VICVectPriority5        VICVectCntl_n(5)
#define VICVectPriority6        VICVectCntl_n(6)
#define VICVectPriority7        VICVectCntl_n(7)
#define VICVectPriority8        VICVectCntl_n(8)
#define VICVectPriority9        VICVectCntl_n(9)
#define VICVectPriority10       VICVectCntl_n(10)
#define VICVectPriority11       VICVectCntl_n(11)
#define VICVectPriority12       VICVectCntl_n(12)
#define VICVectPriority13       VICVectCntl_n(13)
#define VICVectPriority14       VICVectCntl_n(14)
#define VICVectPriority15       VICVectCntl_n(15)
#define VICVectPriority16       VICVectCntl_n(16)
#define VICVectPriority17       VICVectCntl_n(17)
#define VICVectPriority18       VICVectCntl_n(18)
#define VICVectPriority19       VICVectCntl_n(19)
#define VICVectPriority20       VICVectCntl_n(20)
#define VICVectPriority21       VICVectCntl_n(21)
#define VICVectPriority22       VICVectCntl_n(22)
#define VICVectPriority23       VICVectCntl_n(23)
#define VICVectPriority24       VICVectCntl_n(24)
#define VICVectPriority25       VICVectCntl_n(25)
#define VICVectPriority26       VICVectCntl_n(26)
#define VICVectPriority27       VICVectCntl_n(27)
#define VICVectPriority28       VICVectCntl_n(28)
#define VICVectPriority29       VICVectCntl_n(29)
#define VICVectPriority30       VICVectCntl_n(30)
#define VICVectPriority31       VICVectCntl_n(31)

#if ((i_MCU_MODEL >= 2100) && (i_MCU_MODEL < 2300))
        /*----- strange registers--------*/
        #define VICITCR         (*(REG32*)(VIC_BASE + 0x300))
        #define VICITIP1        (*(REG32*)(VIC_BASE + 0x304))
        #define VICITIP2        (*(REG32*)(VIC_BASE + 0x308))
        #define VICITOP1        (*(REG32*)(VIC_BASE + 0x30C))
        #define VICITOP2        (*(REG32*)(VIC_BASE + 0x310))
        #define VICPeriphID0    (*(REG32*)(VIC_BASE + 0xFE0))
        #define VICPeriphID1    (*(REG32*)(VIC_BASE + 0xFE4))
        #define VICPeriphID2    (*(REG32*)(VIC_BASE + 0xFE8))
        #define VICPeriphID3    (*(REG32*)(VIC_BASE + 0xFEc))
#endif
/*-------------System Control Block(SCB)--------------------------------------*/
/* System Control Block(SCB) modules include
        Memory Accelerator Module,
        Phase Locked Loop,
        VPB divider,
        Power Control,
        External Interrupt,
        Reset, and
        Code Security/Debugging
         */
#define SCB_BASE        0xE01FC000

/* Memory Accelerator Module (MAM) */
#define MAMCR           (*(REG32*)(SCB_BASE + 0x000))
#define MAMTIM          (*(REG32*)(SCB_BASE + 0x004))
#define MEMMAP          (*(REG32*)(SCB_BASE + 0x040))

/* Phase Locked Loop (PLL) */
#define PLLCON          (*(REG32*)(SCB_BASE + 0x080))
#define PLLCFG          (*(REG32*)(SCB_BASE + 0x084))
#define PLLSTAT         (*(REG32*)(SCB_BASE + 0x088))
#define PLLFEED         (*(REG32*)(SCB_BASE + 0x08C))

/* Power Control */
#define PCON            (*(REG32*)(SCB_BASE + 0x0C0))
#define PCONP           (*(REG32*)(SCB_BASE + 0x0C4))

/** \brief TURN ON PERIPHIRAL MODULE in NXP controller
 */
#define  PORT_LPC2XXX_PWR_CONTRL_ON(num)        PCONP = PCONP | (1 <<(num##_lpc_periph))
#define  PORT_LPC2XXX_PWR_CONTRL_OFF(num)       PCONP = PCONP & (~(1 <<(num##_lpc_periph)))

/* Clock Divider */
#define APBDIV          (*(REG32*)(SCB_BASE + 0x100))
#define CCLKCFG         (*(REG32*)(SCB_BASE + 0x104))
#define USBCLKCFG       (*(REG32*)(SCB_BASE + 0x108))
#define CLKSRCSEL       (*(REG32*)(SCB_BASE + 0x10C))
#define PCLKSEL0        (*(REG32*)(SCB_BASE + 0x1A8))
#define PCLKSEL1        (*(REG32*)(SCB_BASE + 0x1AC))

/* External Interrupts */
#define EXTINT          (*(REG32*)(SCB_BASE + 0x140))
#define INTWAKE         (*(REG32*)(SCB_BASE + 0x144))
#define EXTMODE         (*(REG32*)(SCB_BASE + 0x148))
#define EXTPOLAR                (*(REG32*)(SCB_BASE + 0x14C))

/* Reset, reset source identification */
#define RSID            (*(REG32*)(SCB_BASE + 0x180))

/* RSID, code security protection */
#define CSPR            (*(REG32*)(SCB_BASE + 0x184))

/* AHB configuration */
#define AHBCFG1         (*(REG32*)(SCB_BASE + 0x188))
#define AHBCFG2         (*(REG32*)(SCB_BASE + 0x18C))

/* System Controls and Status */
#define SCS             (*(REG32*)(SCB_BASE + 0x1A0))

/*-------------TIMERS---------------------------------------------------------*/
#define IR_Off          0x00
#define TCR_Off         0x04
#define TC_Off          0x08
#define PR_Off          0x0C
#define PC_Off          0x10
#define MCR_Off         0x14
#define MR0_Off         0x18
#define MR1_Off         0x1C
#define MR2_Off         0x20
#define MR3_Off         0x24
#define CCR_Off         0x28
#define CR0_Off         0x2C
#define CR1_Off         0x30
#define CR2_Off         0x34
#define CR3_Off         0x38
#define EMR_Off         0x3C
#define CTCR_Off        0x70

#ifndef LPC_T0_BASE
        #define LPC_T0_BASE LPC_TIM0_BASE
#endif
#ifndef LPC_T1_BASE
        #define LPC_T1_BASE LPC_TIM1_BASE
#endif
#ifndef LPC_T2_BASE
        #define LPC_T2_BASE LPC_TIM2_BASE
#endif
#ifndef LPC_T3_BASE
        #define LPC_T3_BASE LPC_TIM3_BASE
#endif

#define T0IR    VBP_REG32(T0,IR)
#define T0TCR   VBP_REG32(T0,TCR)
#define T0TC    VBP_REG32(T0,TC)
#define T0PR    VBP_REG32(T0,PR)
#define T0PC    VBP_REG32(T0,PC)
#define T0MCR   VBP_REG32(T0,MCR)
#define T0MR0   VBP_REG32(T0,MR0)
#define T0MR1   VBP_REG32(T0,MR1)
#define T0MR2   VBP_REG32(T0,MR2)
#define T0MR3   VBP_REG32(T0,MR3)
#define T0CCR   VBP_REG32(T0,CCR)
#define T0CR0   VBP_REG32(T0,CR0)
#define T0CR1   VBP_REG32(T0,CR1)
#define T0CR2   VBP_REG32(T0,CR2)
#define T0CR3   VBP_REG32(T0,CR3)
#define T0EMR   VBP_REG32(T0,EMR)
#define T0CTCR  VBP_REG32(T0,CTCR)

#define T1IR    VBP_REG32(T1,IR)
#define T1TCR   VBP_REG32(T1,TCR)
#define T1TC    VBP_REG32(T1,TC)
#define T1PR    VBP_REG32(T1,PR)
#define T1PC    VBP_REG32(T1,PC)
#define T1MCR   VBP_REG32(T1,MCR)
#define T1MR0   VBP_REG32(T1,MR0)
#define T1MR1   VBP_REG32(T1,MR1)
#define T1MR2   VBP_REG32(T1,MR2)
#define T1MR3   VBP_REG32(T1,MR3)
#define T1CCR   VBP_REG32(T1,CCR)
#define T1CR0   VBP_REG32(T1,CR0)
#define T1CR1   VBP_REG32(T1,CR1)
#define T1CR2   VBP_REG32(T1,CR2)
#define T1CR3   VBP_REG32(T1,CR3)
#define T1EMR   VBP_REG32(T1,EMR)
#define T1CTCR  VBP_REG32(T1,CTCR)

#define T2IR    VBP_REG32(T2,IR)
#define T2TCR   VBP_REG32(T2,TCR)
#define T2TC    VBP_REG32(T2,TC)
#define T2PR    VBP_REG32(T2,PR)
#define T2PC    VBP_REG32(T2,PC)
#define T2MCR   VBP_REG32(T2,MCR)
#define T2MR0   VBP_REG32(T2,MR0)
#define T2MR1   VBP_REG32(T2,MR1)
#define T2MR2   VBP_REG32(T2,MR2)
#define T2MR3   VBP_REG32(T2,MR3)
#define T2CCR   VBP_REG32(T2,CCR)
#define T2CR0   VBP_REG32(T2,CR0)
#define T2CR1   VBP_REG32(T2,CR1)
#define T2CR2   VBP_REG32(T2,CR2)
#define T2CR3   VBP_REG32(T2,CR3)
#define T2EMR   VBP_REG32(T2,EMR)
#define T2CTCR  VBP_REG32(T2,CTCR)

#define T3IR    VBP_REG32(T3,IR)
#define T3TCR   VBP_REG32(T3,TCR)
#define T3TC    VBP_REG32(T3,TC)
#define T3PR    VBP_REG32(T3,PR)
#define T3PC    VBP_REG32(T3,PC)
#define T3MCR   VBP_REG32(T3,MCR)
#define T3MR0   VBP_REG32(T3,MR0)
#define T3MR1   VBP_REG32(T3,MR1)
#define T3MR2   VBP_REG32(T3,MR2)
#define T3MR3   VBP_REG32(T3,MR3)
#define T3CCR   VBP_REG32(T3,CCR)
#define T3CR0   VBP_REG32(T3,CR0)
#define T3CR1   VBP_REG32(T3,CR1)
#define T3CR2   VBP_REG32(T3,CR2)
#define T3CR3   VBP_REG32(T3,CR3)
#define T3EMR   VBP_REG32(T3,EMR)
#define T3CTCR  VBP_REG32(T3,CTCR)

/*-------------Pulse Width Modulator (PWM) -----------------------------------*/
/*  */
#define PWM0IR          (*(REG32 *)(LPC_PWM0_BASE + 0x00))
#define PWM0TCR         (*(REG32 *)(LPC_PWM0_BASE + 0x04))
#define PWM0TC          (*(REG32 *)(LPC_PWM0_BASE + 0x08))
#define PWM0PR          (*(REG32 *)(LPC_PWM0_BASE + 0x0C))
#define PWM0PC          (*(REG32 *)(LPC_PWM0_BASE + 0x10))
#define PWM0MCR         (*(REG32 *)(LPC_PWM0_BASE + 0x14))
#define PWM0MR0         (*(REG32 *)(LPC_PWM0_BASE + 0x18))
#define PWM0MR1         (*(REG32 *)(LPC_PWM0_BASE + 0x1C))
#define PWM0MR2         (*(REG32 *)(LPC_PWM0_BASE + 0x20))
#define PWM0MR3         (*(REG32 *)(LPC_PWM0_BASE + 0x24))
#define PWM0CCR         (*(REG32 *)(LPC_PWM0_BASE + 0x28))
#define PWM0CR0         (*(REG32 *)(LPC_PWM0_BASE + 0x2C))
#define PWM0CR1         (*(REG32 *)(LPC_PWM0_BASE + 0x30))
#define PWM0CR2         (*(REG32 *)(LPC_PWM0_BASE + 0x34))
#define PWM0CR3         (*(REG32 *)(LPC_PWM0_BASE + 0x38))
#define PWM0EMR         (*(REG32 *)(LPC_PWM0_BASE + 0x3C))
#define PWM0MR4         (*(REG32 *)(LPC_PWM0_BASE + 0x40))
#define PWM0MR5         (*(REG32 *)(LPC_PWM0_BASE + 0x44))
#define PWM0MR6         (*(REG32 *)(LPC_PWM0_BASE + 0x48))
#define PWM0PCR         (*(REG32 *)(LPC_PWM0_BASE + 0x4C))
#define PWM0LER         (*(REG32 *)(LPC_PWM0_BASE + 0x50))
#define PWM0CTCR        (*(REG32 *)(LPC_PWM0_BASE + 0x70))

#define PWM1IR          (*(REG32 *)(LPC_PWM1_BASE + 0x00))
#define PWM1TCR         (*(REG32 *)(LPC_PWM1_BASE + 0x04))
#define PWM1TC          (*(REG32 *)(LPC_PWM1_BASE + 0x08))
#define PWM1PR          (*(REG32 *)(LPC_PWM1_BASE + 0x0C))
#define PWM1PC          (*(REG32 *)(LPC_PWM1_BASE + 0x10))
#define PWM1MCR         (*(REG32 *)(LPC_PWM1_BASE + 0x14))
#define PWM1MR0         (*(REG32 *)(LPC_PWM1_BASE + 0x18))
#define PWM1MR1         (*(REG32 *)(LPC_PWM1_BASE + 0x1C))
#define PWM1MR2         (*(REG32 *)(LPC_PWM1_BASE + 0x20))
#define PWM1MR3         (*(REG32 *)(LPC_PWM1_BASE + 0x24))
#define PWM1CCR         (*(REG32 *)(LPC_PWM1_BASE + 0x28))
#define PWM1CR0         (*(REG32 *)(LPC_PWM1_BASE + 0x2C))
#define PWM1CR1         (*(REG32 *)(LPC_PWM1_BASE + 0x30))
#define PWM1CR2         (*(REG32 *)(LPC_PWM1_BASE + 0x34))
#define PWM1CR3         (*(REG32 *)(LPC_PWM1_BASE + 0x38))
#define PWM1EMR         (*(REG32 *)(LPC_PWM1_BASE + 0x3C))
#define PWM1MR4         (*(REG32 *)(LPC_PWM1_BASE + 0x40))
#define PWM1MR5         (*(REG32 *)(LPC_PWM1_BASE + 0x44))
#define PWM1MR6         (*(REG32 *)(LPC_PWM1_BASE + 0x48))
#define PWM1PCR         (*(REG32 *)(LPC_PWM1_BASE + 0x4C))
#define PWM1LER         (*(REG32 *)(LPC_PWM1_BASE + 0x50))
#define PWM1CTCR        (*(REG32 *)(LPC_PWM1_BASE + 0x70))

/*-------------PINS-----------------------------------------------------------*/
#define PINSEL_n(n)     (*(REG32*)(LPC_PINSEL_BASE + (n<<2))) /**< get PINSEL REG */

#define LPC2XXX_PORT0   0
#define LPC2XXX_PORT1   1
#define LPC2XXX_PORT2   2
#define LPC2XXX_PORT3   3
#define LPC2XXX_PORT4   4

/**
 *\if russian_lng
 *      Вычислить общий номер ножки согласно номеру порта и ножки
 *\else
 *      Calculate common pin number accoding to number of port and pin
 *\endif
\code
        #define UART_1_TX_PIN_NUMBER    PORT_PIN_NUMBER(PORT3,16)
        #define UART_1_RX_PIN_NUMBER    PORT_PIN_NUMBER(PORT3,17)
\endcode
 */
#define PORT_PIN_NUMBER(prt,number)     (prt*32+number)

/**
 *\if russian_lng
 *      Установать вывод ножки номер number согласно value
 *
 *      P0[0] имеет номер 0, P1[0] имеет номер 32,  P2[2] имеет номер 2*32+2=64 и т.д
 *\else
 *      Set pin accoding to pin number (number) and its mode (value)
 *
 *      P0[0] has number0, P1[0] has number 32,  P2[2] has number 2*32+2=64 and so on
 *\endif

\code
        PORT_SELECT_PIN (UART_1_TX_PIN_NUMBER,  UART_1_TX_PIN_SELECT);
        PORT_SELECT_PIN (UART_1_RX_PIN_NUMBER,  UART_1_RX_PIN_SELECT);
\endcode
 */
#define PORT_SELECT_PIN(number,value)   PINSEL_n(number>>4) = \
                (PINSEL_n(number>>4) & (~(3<<((number&0xf)<<1)))) | ((value&3)<<((number&0xf)<<1))

/** By default 0 configures GP IO*/
#define PORT_PIN_MODE_GPIO      0
/*-------------PINS-----------------------------------------------------------*/
#define PINSEL0         PINSEL_n(0)
#define PINSEL1         PINSEL_n(1)
#define PINSEL2         PINSEL_n(2)
#define PINSEL3         PINSEL_n(3)
#define PINSEL4         PINSEL_n(4)
#define PINSEL5         PINSEL_n(5)
#define PINSEL6         PINSEL_n(6)
#define PINSEL7         PINSEL_n(7)
#define PINSEL8         PINSEL_n(8)
#define PINSEL9         PINSEL_n(9)
#define PINSEL10        PINSEL_n(10)

#define PINMODE_n(n)    (*(REG32*)(LPC_PINSEL_BASE + 0x40 + (n<<2)))
#define PINMODE0        PINMODE_n(0)
#define PINMODE1        PINMODE_n(1)
#define PINMODE2        PINMODE_n(2)
#define PINMODE3        PINMODE_n(3)
#define PINMODE4        PINMODE_n(4)
#define PINMODE5        PINMODE_n(5)
#define PINMODE6        PINMODE_n(6)
#define PINMODE7        PINMODE_n(7)
#define PINMODE8        PINMODE_n(8)
#define PINMODE9        PINMODE_n(9)
#define PINMODE10       PINMODE_n(10)

#define PINMODE_PULL_UP         0
#define PINMODE_DEFAULT         PINMODE_PULL_UP
#define PINMODE_NO_PULL_        2
#define PINMODE_PULL_DOWN       3


/*-------------General Purpose Input/Output (GPIO)----------------------------*/
#define GPIO_BASE LPC_GPIO_BASE
#define IOPIN0          (*(REG32*)(GPIO_BASE + 0x00))
#define IOSET0          (*(REG32*)(GPIO_BASE + 0x04))
#define IODIR0          (*(REG32*)(GPIO_BASE + 0x08))
#define IOCLR0          (*(REG32*)(GPIO_BASE + 0x0C))
#define IOPIN1          (*(REG32*)(GPIO_BASE + 0x10))
#define IOSET1          (*(REG32*)(GPIO_BASE + 0x14))
#define IODIR1          (*(REG32*)(GPIO_BASE + 0x18))
#define IOCLR1          (*(REG32*)(GPIO_BASE + 0x1C))

#define IOPIN   IOPIN0
#define IOSET   IOSET0
#define IODIR   IODIR0
#define IOCLR   IOCLR0

/*-------------GPIO Interrupt Registers --------------------------------------*/
#define IO0_INT_EN_R            (*(REG32*)(GPIO_BASE + 0x90))
#define IO0_INT_EN_F            (*(REG32*)(GPIO_BASE + 0x94))
#define IO0_INT_STAT_R          (*(REG32*)(GPIO_BASE + 0x84))
#define IO0_INT_STAT_F          (*(REG32*)(GPIO_BASE + 0x88))
#define IO0_INT_CLR             (*(REG32*)(GPIO_BASE + 0x8C))

#define IO2_INT_EN_R            (*(REG32*)(GPIO_BASE + 0xB0))
#define IO2_INT_EN_F            (*(REG32*)(GPIO_BASE + 0xB4))
#define IO2_INT_STAT_R          (*(REG32*)(GPIO_BASE + 0xA4))
#define IO2_INT_STAT_F          (*(REG32*)(GPIO_BASE + 0xA8))
#define IO2_INT_CLR             (*(REG32*)(GPIO_BASE + 0xAC))

#define IO_INT_STAT             (*(REG32*)(GPIO_BASE + 0x80))

#define PARTCFG                 (*(REG32*)(PARTCFG_BASE + 0x00))
/*-------------Fast I/O setup   ----------------------------------------------*/
#define FIOREG_BASE_ADDR_n(n,off)       (*(REG32*)(LPC_FIO_BASE + (n<<5)+ off))
#define FIOREG_BASE_ADDR_n16(n,off)     (*(REG16*)(LPC_FIO_BASE + (n<<5)+ off))
#define FIOREG_BASE_ADDR_n8(n,off)      (*(REG8*)(LPC_FIO_BASE + (n<<5)+ off))

#define FIO0DIR         FIOREG_BASE_ADDR_n(0,0)
#define FIO0MASK        FIOREG_BASE_ADDR_n(0,0x10)
#define FIO0PIN         FIOREG_BASE_ADDR_n(0,0x14)
#define FIO0SET         FIOREG_BASE_ADDR_n(0,0x18)
#define FIO0CLR         FIOREG_BASE_ADDR_n(0,0x1C)

/**FIO DIR CONSTANT TO MAKE PORT BE INPUT*/
#define PIN_INPUT       0
/**FIO DIR CONSTANT TO MAKE PORT BE OUTPUT*/
#define PIN_OUTPUT      1
/** SET PIN DIRECTION (PIN_OUTPUT or PIN_INPUT )*/
#define PORT_DIRECTION_PIN(number,direction)    \
                        FIOREG_BASE_ADDR_n(((number)>>5),0x00) |= 1 << ((number)&0x1F); \
                        if ((number>>6) == 0){          \
                                SCS |= 1;};
                        /* port0 and port1 turning to new scheme*/

/** SET PIN TO HIGHT LEVEL (IF DIRECTION IS PIN_OUTPUT )*/
#define PORT_SET_PIN(number)    \
                        FIOREG_BASE_ADDR_n(((number)>>5),0x18) = 1 << ((number)&0x1F)
/** SET PIN TO LOW LEVEL (IF DIRECTION IS PIN_OUTPUT )*/
#define PORT_CLEAR_PIN(number)  \
                        FIOREG_BASE_ADDR_n(((number)>>5),0x1C) = 1 << ((number)&0x1F)
/** GET VALUE OF PIN*/
#define PORT_GET_PIN(number)    \
                        (FIOREG_BASE_ADDR_n(((number)>>5),0x14) &(1 << ((number)&0x1F)))

#define FIO1DIR         FIOREG_BASE_ADDR_n(1,0)
#define FIO1MASK        FIOREG_BASE_ADDR_n(1,0x10)
#define FIO1PIN         FIOREG_BASE_ADDR_n(1,0x14)
#define FIO1SET         FIOREG_BASE_ADDR_n(1,0x18)
#define FIO1CLR         FIOREG_BASE_ADDR_n(1,0x1C)

#define FIO2DIR         FIOREG_BASE_ADDR_n(2,0)
#define FIO2MASK        FIOREG_BASE_ADDR_n(2,0x10)
#define FIO2PIN         FIOREG_BASE_ADDR_n(2,0x14)
#define FIO2SET         FIOREG_BASE_ADDR_n(2,0x18)
#define FIO2CLR         FIOREG_BASE_ADDR_n(2,0x1C)

#define FIO3DIR         FIOREG_BASE_ADDR_n(3,0)
#define FIO3MASK        FIOREG_BASE_ADDR_n(3,0x10)
#define FIO3PIN         FIOREG_BASE_ADDR_n(3,0x14)
#define FIO3SET         FIOREG_BASE_ADDR_n(3,0x18)
#define FIO3CLR         FIOREG_BASE_ADDR_n(3,0x1C)

#define FIO4DIR         FIOREG_BASE_ADDR_n(4,0)
#define FIO4MASK        FIOREG_BASE_ADDR_n(4,0x10)
#define FIO4PIN         FIOREG_BASE_ADDR_n(4,0x14)
#define FIO4SET         FIOREG_BASE_ADDR_n(4,0x18)
#define FIO4CLR         FIOREG_BASE_ADDR_n(4,0x1C)


/* FIOs can be accessed throughFIOREG_BASE_ADDR_n8 WORD, HALF-WORD or BYTE. */
#define FIO0DIR0        FIOREG_BASE_ADDR_n8(0,0)
#define FIO1DIR0        FIOREG_BASE_ADDR_n8(1,0)
#define FIO2DIR0        FIOREG_BASE_ADDR_n8(2,0)
#define FIO3DIR0        FIOREG_BASE_ADDR_n8(3,0)
#define FIO4DIR0        FIOREG_FIOREG_BASE_ADDR_n8BASE_ADDR_n8(4,0)

#define FIO0DIR1        FIOREG_BASE_ADDR_n8(0,1)
#define FIO1DIR1        FIOREG_BASE_ADDR_n8(1,1)
#define FIO2DIR1        FIOREG_BASE_ADDR_n8(2,1)
#define FIO3DIR1        FIOREG_BASE_ADDR_n8(3,1)
#define FIO4DIR1        FIOREG_BASE_ADDR_n8(4,1)

#define FIO0DIR2        FIOREG_BASE_ADDR_n8(0,2)
#define FIO1DIR2        FIOREG_BASE_ADDR_n8(1,2)
#define FIO2DIR2        FIOREG_BASE_ADDR_n8(2,2)
#define FIO3DIR2        FIOREG_BASE_ADDR_n8(3,2)
#define FIO4DIR2        FIOREG_BASE_ADDR_n8(4,2)

#define FIO0DIR3        FIOREG_BASE_ADDR_n8(0,3)
#define FIO1DIR3        FIOREG_BASE_ADDR_n8(1,3)
#define FIO2DIR3        FIOREG_BASE_ADDR_n8(2,3)
#define FIO3DIR3        FIOREG_BASE_ADDR_n8(3,3)
#define FIO4DIR3        FIOREG_BASE_ADDR_n8(4,3)

#define FIO0DIRL        FIOREG_BASE_ADDR_n16(0,0)
#define FIO1DIRL        FIOREG_BASE_ADDR_n16(1,0)
#define FIO2DIRL        FIOREG_BASE_ADDR_n16(2,0)
#define FIO3DIRL        FIOREG_BASE_ADDR_n16(3,0)
#define FIO4DIRL        FIOREG_BASE_ADDR_n16(4,0)

#define FIO0DIRU        FIOREG_BASE_ADDR_n16(0,2)
#define FIO1DIRU        FIOREG_BASE_ADDR_n16(1,2)
#define FIO2DIRU        FIOREG_BASE_ADDR_n16(2,2)
#define FIO3DIRU        FIOREG_BASE_ADDR_n16(3,2)
#define FIO4DIRU        FIOREG_BASE_ADDR_n16(4,2)
/*-----------------*/
#define FIOREG_BASE_ADDR_n8_FIOMASK(letter1,letter2)    \
        FIOREG_BASE_ADDR_n8(letter1,0x10+letter2)

#define FIO0MASK0       FIOREG_BASE_ADDR_n8_FIOMASK(0,0)
#define FIO1MASK0       FIOREG_BASE_ADDR_n8_FIOMASK(1,0)
#define FIO2MASK0       FIOREG_BASE_ADDR_n8_FIOMASK(2,0)
#define FIO3MASK0       FIOREG_BASE_ADDR_n8_FIOMASK(3,0)
#define FIO4MASK0       FIOREG_BASE_ADDR_n8_FIOMASK(4,0)

#define FIO0MASK1       FIOREG_BASE_ADDR_n8_FIOMASK(0,1)
#define FIO1MASK1       FIOREG_BASE_ADDR_n8_FIOMASK(1,1)
#define FIO2MASK1       FIOREG_BASE_ADDR_n8_FIOMASK(2,1)
#define FIO3MASK1       FIOREG_BASE_ADDR_n8_FIOMASK(3,1)
#define FIO4MASK1       FIOREG_BASE_ADDR_n8_FIOMASK(4,1)

#define FIO0MASK2       FIOREG_BASE_ADDR_n8_FIOMASK(0,2)
#define FIO1MASK2       FIOREG_BASE_ADDR_n8_FIOMASK(1,2)
#define FIO2MASK2       FIOREG_BASE_ADDR_n8_FIOMASK(2,2)
#define FIO3MASK2       FIOREG_BASE_ADDR_n8_FIOMASK(3,2)
#define FIO4MASK2       FIOREG_BASE_ADDR_n8_FIOMASK(4,2)

#define FIO0MASK3       FIOREG_BASE_ADDR_n8_FIOMASK(0,3)
#define FIO1MASK3       FIOREG_BASE_ADDR_n8_FIOMASK(1,3)
#define FIO2MASK3       FIOREG_BASE_ADDR_n8_FIOMASK(2,3)
#define FIO3MASK3       FIOREG_BASE_ADDR_n8_FIOMASK(3,3)
#define FIO4MASK3       FIOREG_BASE_ADDR_n8_FIOMASK(4,3)
/*-----------------*/
#define FIOREG_BASE_ADDR_n16_FIOMASKL(letter1)  \
        FIOREG_BASE_ADDR_n16(letter1,0x10)

#define FIOREG_BASE_ADDR_n16_FIOMASKU(letter1)  \
        FIOREG_BASE_ADDR_n16(letter1,0x12)

#define FIO0MASKL       FIOREG_BASE_ADDR_n16_FIOMASKL(0)
#define FIO1MASKL       FIOREG_BASE_ADDR_n16_FIOMASKL(1)
#define FIO2MASKL       FIOREG_BASE_ADDR_n16_FIOMASKL(2)
#define FIO3MASKL       FIOREG_BASE_ADDR_n16_FIOMASKL(3)
#define FIO4MASKL       FIOREG_BASE_ADDR_n16_FIOMASKL(4)

#define FIO0MASKU       FIOREG_BASE_ADDR_n16_FIOMASKU(0)
#define FIO1MASKU       FIOREG_BASE_ADDR_n16_FIOMASKU(1)
#define FIO2MASKU       FIOREG_BASE_ADDR_n16_FIOMASKU(2)
#define FIO3MASKU       FIOREG_BASE_ADDR_n16_FIOMASKU(3)
#define FIO4MASKU       FIOREG_BASE_ADDR_n16_FIOMASKU(4)
/*-----------------*/   /*-----------------*/
#define FIO_BASE        LPC_FIO_BASE
#define FIO0PIN0       (*(volatile unsigned char *)(FIO_BASE + 0x14))
#define FIO1PIN0       (*(volatile unsigned char *)(FIO_BASE + 0x34))
#define FIO2PIN0       (*(volatile unsigned char *)(FIO_BASE + 0x54))
#define FIO3PIN0       (*(volatile unsigned char *)(FIO_BASE + 0x74))
#define FIO4PIN0       (*(volatile unsigned char *)(FIO_BASE + 0x94))

#define FIO0PIN1       (*(volatile unsigned char *)(FIO_BASE + 0x15))
#define FIO1PIN1       (*(volatile unsigned char *)(FIO_BASE + 0x35))
#define FIO2PIN1       (*(volatile unsigned char *)(FIO_BASE + 0x55))
#define FIO3PIN1       (*(volatile unsigned char *)(FIO_BASE + 0x75))
#define FIO4PIN1       (*(volatile unsigned char *)(FIO_BASE + 0x95))

#define FIO0PIN2       (*(volatile unsigned char *)(FIO_BASE + 0x16))
#define FIO1PIN2       (*(volatile unsigned char *)(FIO_BASE + 0x36))
#define FIO2PIN2       (*(volatile unsigned char *)(FIO_BASE + 0x56))
#define FIO3PIN2       (*(volatile unsigned char *)(FIO_BASE + 0x76))
#define FIO4PIN2       (*(volatile unsigned char *)(FIO_BASE + 0x96))

#define FIO0PIN3       (*(volatile unsigned char *)(FIO_BASE + 0x17))
#define FIO1PIN3       (*(volatile unsigned char *)(FIO_BASE + 0x37))
#define FIO2PIN3       (*(volatile unsigned char *)(FIO_BASE + 0x57))
#define FIO3PIN3       (*(volatile unsigned char *)(FIO_BASE + 0x77))
#define FIO4PIN3       (*(volatile unsigned char *)(FIO_BASE + 0x97))

#define FIO0PINL       (*(volatile unsigned short *)(FIO_BASE + 0x14))
#define FIO1PINL       (*(volatile unsigned short *)(FIO_BASE + 0x34))
#define FIO2PINL       (*(volatile unsigned short *)(FIO_BASE + 0x54))
#define FIO3PINL       (*(volatile unsigned short *)(FIO_BASE + 0x74))
#define FIO4PINL       (*(volatile unsigned short *)(FIO_BASE + 0x94))

#define FIO0PINU       (*(volatile unsigned short *)(FIO_BASE + 0x16))
#define FIO1PINU       (*(volatile unsigned short *)(FIO_BASE + 0x36))
#define FIO2PINU       (*(volatile unsigned short *)(FIO_BASE + 0x56))
#define FIO3PINU       (*(volatile unsigned short *)(FIO_BASE + 0x76))
#define FIO4PINU       (*(volatile unsigned short *)(FIO_BASE + 0x96))

#define FIO0SET0       (*(volatile unsigned char *)(FIO_BASE + 0x18))
#define FIO1SET0       (*(volatile unsigned char *)(FIO_BASE + 0x38))
#define FIO2SET0       (*(volatile unsigned char *)(FIO_BASE + 0x58))
#define FIO3SET0       (*(volatile unsigned char *)(FIO_BASE + 0x78))
#define FIO4SET0       (*(volatile unsigned char *)(FIO_BASE + 0x98))

#define FIO0SET1       (*(volatile unsigned char *)(FIO_BASE + 0x19))
#define FIO1SET1       (*(volatile unsigned char *)(FIO_BASE + 0x29))
#define FIO2SET1       (*(volatile unsigned char *)(FIO_BASE + 0x59))
#define FIO3SET1       (*(volatile unsigned char *)(FIO_BASE + 0x79))
#define FIO4SET1       (*(volatile unsigned char *)(FIO_BASE + 0x99))

#define FIO0SET2       (*(volatile unsigned char *)(FIO_BASE + 0x1A))
#define FIO1SET2       (*(volatile unsigned char *)(FIO_BASE + 0x3A))
#define FIO2SET2       (*(volatile unsigned char *)(FIO_BASE + 0x5A))
#define FIO3SET2       (*(volatile unsigned char *)(FIO_BASE + 0x7A))
#define FIO4SET2       (*(volatile unsigned char *)(FIO_BASE + 0x9A))

#define FIO0SET3       (*(volatile unsigned char *)(FIO_BASE + 0x1B))
#define FIO1SET3       (*(volatile unsigned char *)(FIO_BASE + 0x3B))
#define FIO2SET3       (*(volatile unsigned char *)(FIO_BASE + 0x5B))
#define FIO3SET3       (*(volatile unsigned char *)(FIO_BASE + 0x7B))
#define FIO4SET3       (*(volatile unsigned char *)(FIO_BASE + 0x9B))

#define FIO0SETL       (*(volatile unsigned short *)(FIO_BASE + 0x18))
#define FIO1SETL       (*(volatile unsigned short *)(FIO_BASE + 0x38))
#define FIO2SETL       (*(volatile unsigned short *)(FIO_BASE + 0x58))
#define FIO3SETL       (*(volatile unsigned short *)(FIO_BASE + 0x78))
#define FIO4SETL       (*(volatile unsigned short *)(FIO_BASE + 0x98))

#define FIO0SETU       (*(volatile unsigned short *)(FIO_BASE + 0x1A))
#define FIO1SETU       (*(volatile unsigned short *)(FIO_BASE + 0x3A))
#define FIO2SETU       (*(volatile unsigned short *)(FIO_BASE + 0x5A))
#define FIO3SETU       (*(volatile unsigned short *)(FIO_BASE + 0x7A))
#define FIO4SETU       (*(volatile unsigned short *)(FIO_BASE + 0x9A))

#define FIO0CLR0       (*(volatile unsigned char *)(FIO_BASE + 0x1C))
#define FIO1CLR0       (*(volatile unsigned char *)(FIO_BASE + 0x3C))
#define FIO2CLR0       (*(volatile unsigned char *)(FIO_BASE + 0x5C))
#define FIO3CLR0       (*(volatile unsigned char *)(FIO_BASE + 0x7C))
#define FIO4CLR0       (*(volatile unsigned char *)(FIO_BASE + 0x9C))

#define FIO0CLR1       (*(volatile unsigned char *)(FIO_BASE + 0x1D))
#define FIO1CLR1       (*(volatile unsigned char *)(FIO_BASE + 0x2D))
#define FIO2CLR1       (*(volatile unsigned char *)(FIO_BASE + 0x5D))
#define FIO3CLR1       (*(volatile unsigned char *)(FIO_BASE + 0x7D))
#define FIO4CLR1       (*(volatile unsigned char *)(FIO_BASE + 0x9D))

#define FIO0CLR2       (*(volatile unsigned char *)(FIO_BASE + 0x1E))
#define FIO1CLR2       (*(volatile unsigned char *)(FIO_BASE + 0x3E))
#define FIO2CLR2       (*(volatile unsigned char *)(FIO_BASE + 0x5E))
#define FIO3CLR2       (*(volatile unsigned char *)(FIO_BASE + 0x7E))
#define FIO4CLR2       (*(volatile unsigned char *)(FIO_BASE + 0x9E))

#define FIO0CLR3       (*(volatile unsigned char *)(FIO_BASE + 0x1F))
#define FIO1CLR3       (*(volatile unsigned char *)(FIO_BASE + 0x3F))
#define FIO2CLR3       (*(volatile unsigned char *)(FIO_BASE + 0x5F))
#define FIO3CLR3       (*(volatile unsigned char *)(FIO_BASE + 0x7F))
#define FIO4CLR3       (*(volatile unsigned char *)(FIO_BASE + 0x9F))

#define FIO0CLRU       (*(volatile unsigned short *)(FIO_BASE + 0x1E))
#define FIO1CLRU       (*(volatile unsigned short *)(FIO_BASE + 0x3E))
#define FIO2CLRU       (*(volatile unsigned short *)(FIO_BASE + 0x5E))
#define FIO3CLRU       (*(volatile unsigned short *)(FIO_BASE + 0x7E))
#define FIO4CLRU       (*(volatile unsigned short *)(FIO_BASE + 0x9E))

/* \todo Migrating to the LPC2300/2400 family
The following key improvements have been done to the VIC:
1.  VIC register accesses are now controlled by software using the Protection Enable
register (VICProtection-0xFFFF F020). This register is accessible only in an ARM
privileged mode.
2.  The VICAddress register resides in a new location in memory, i.e. 0xFFFF FF00.
Hence the IRQ interrupt vector (residing at 0x18) should now be modified as:
    LDR     PC, [PC, # -0x0120]
      Previously, the instruction would be:
    LDR     PC, [PC, # -0x0FF0]
3.  Spurious interrupts can no longer occur in the LPC23xx/LPC24xx. Hence the Default
Address Register is no longer available in this family.
 */
/*------Universal Asynchronous Receiver PINS (UART0)--------------------------*/
#ifndef UART_0_TX_PIN_NUMBER
#if i_MCU_MODEL >= 2300
        #define UART_0_TX_PIN_NUMBER    PORT_PIN_NUMBER(LPC2XXX_PORT0,2)/**< PINSEL0 Mask for UART0 */
#else
        #define UART_0_TX_PIN_NUMBER    PORT_PIN_NUMBER(LPC2XXX_PORT0,0)/**< PINSEL0 Mask for UART0 */

#endif
#endif
#ifndef UART_0_RX_PIN_NUMBER
#define UART_0_RX_PIN_NUMBER    (UART_0_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART0*/
#endif
#ifndef UART_0_TX_PIN_SELECT
#define UART_0_TX_PIN_SELECT    1                       /**<PINSEL0 Value for UART0*/
#endif
#ifndef UART_0_RX_PIN_SELECT
#define UART_0_RX_PIN_SELECT    UART_0_TX_PIN_SELECT    /**<PINSEL0 Value for UART0*/
#endif

#ifndef UART_1_TX_PIN_NUMBER
#if i_MCU_MODEL >= 2300
        #define UART_1_TX_PIN_NUMBER    PORT_PIN_NUMBER(LPC2XXX_PORT0,10)/**< PINSEL0 Mask for UART1*/
#else
        #define UART_1_TX_PIN_NUMBER    PORT_PIN_NUMBER(LPC2XXX_PORT0,8)/**< PINSEL0 Mask for UART1*/

#endif
#endif

#ifndef UART_1_RX_PIN_NUMBER
#define UART_1_RX_PIN_NUMBER    (UART_1_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART1*/
#endif
#ifndef UART_1_TX_PIN_SELECT
#define UART_1_TX_PIN_SELECT    1                       /**<PINSEL0 Value for UART1*/
#endif
#ifndef UART_1_RX_PIN_SELECT
#define UART_1_RX_PIN_SELECT    UART_1_TX_PIN_SELECT    /**<PINSEL0 Value for UART1*/
#endif
#if i_MCU_MODEL >= 2300
#ifndef UART_2_TX_PIN_NUMBER
        #define UART_2_TX_PIN_NUMBER    PORT_PIN_NUMBER(LPC2XXX_PORT0,10)/**< PINSEL0 Mask*/
#endif
#ifndef UART_2_RX_PIN_NUMBER
        #define UART_2_RX_PIN_NUMBER    (UART_2_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART0*/
#endif
#ifndef UART_2_TX_PIN_SELECT
        #define UART_2_TX_PIN_SELECT    1                       /**<PINSEL Value for UART1*/
#endif
#ifndef UART_2_RX_PIN_SELECT
        #define UART_2_RX_PIN_SELECT    UART_2_TX_PIN_SELECT    /**<PINSEL0 Value for UART1*/
#endif

#ifndef UART_3_TX_PIN_NUMBER
        #define UART_3_TX_PIN_NUMBER    PORT_PIN_NUMBER(LPC2XXX_PORT0,25)/**< PINSEL0 Mask*/
#endif
#ifndef UART_3_RX_PIN_NUMBER
        #define UART_3_RX_PIN_NUMBER    (UART_3_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART0*/
#endif
#ifndef UART_3_TX_PIN_SELECT
        #define UART_3_TX_PIN_SELECT    3                       /**<PINSEL Value for UART1*/
#endif
#ifndef UART_3_RX_PIN_SELECT
        #define UART_3_RX_PIN_SELECT    UART_3_TX_PIN_SELECT    /**<PINSEL0 Value for UART1*/
#endif


/*------Universal Asynchronous Receiver Transmitter 0 (UART0)-----------------*/
#define UART01_BASE_ADDR(n,off) (*(REG32*)(LPC_UART0_BASE + n*0x4000+ off))
#define UART23_BASE_ADDR(n,off) (*(REG32*)(LPC_UART2_BASE + (n-2)*0x4000+ off))
/* can do more complex macrising*/
#define U0RBR           UART01_BASE_ADDR(0,0x00)
#define U0THR           UART01_BASE_ADDR(0,0x00)
#define U0DLL           UART01_BASE_ADDR(0,0x00)
#define U0DLM           UART01_BASE_ADDR(0,0x04)
#define U0IER           UART01_BASE_ADDR(0,0x04)
#define U0IIR           UART01_BASE_ADDR(0,0x08)
#define U0FCR           UART01_BASE_ADDR(0,0x08)
#define U0LCR           UART01_BASE_ADDR(0,0x0C)
#define U0LSR           UART01_BASE_ADDR(0,0x14)
#define U0SCR           UART01_BASE_ADDR(0,0x1C)
#define U0ACR           UART01_BASE_ADDR(0,0x20)
#define U0ICR           UART01_BASE_ADDR(0,0x24)
#define U0FDR           UART01_BASE_ADDR(0,0x28)
#define U0TER           UART01_BASE_ADDR(0,0x30)
/*------Universal Asynchronous Receiver Transmitter 1 (UART0)-----------------*/
#define U1RBR           UART01_BASE_ADDR(1,0x00)
#define U1THR           UART01_BASE_ADDR(1,0x00)
#define U1DLL           UART01_BASE_ADDR(1,0x00)
#define U1DLM           UART01_BASE_ADDR(1,0x04)
#define U1IER           UART01_BASE_ADDR(1,0x04)
#define U1IIR           UART01_BASE_ADDR(1,0x08)
#define U1FCR           UART01_BASE_ADDR(1,0x08)
#define U1LCR           UART01_BASE_ADDR(1,0x0C)
#define U1MCR           UART01_BASE_ADDR(1,0x10) /* only UART1*/
#define U1LSR           UART01_BASE_ADDR(1,0x14)
#define U1MSR           UART01_BASE_ADDR(1,0x18) /* only UART1*/
#define U1SCR           UART01_BASE_ADDR(1,0x1C)
#define U1ACR           UART01_BASE_ADDR(1,0x20)
#define U1ICR           UART01_BASE_ADDR(1,0x24)
#define U1FDR           UART01_BASE_ADDR(1,0x28)
#define U1TER           UART01_BASE_ADDR(1,0x30)
/*------Universal Asynchronous Receiver Transmitter 2 (UART0)-----------------*/
#define U2RBR           UART23_BASE_ADDR(2,0x00)
#define U2THR           UART23_BASE_ADDR(2,0x00)
#define U2DLL           UART23_BASE_ADDR(2,0x00)
#define U2DLM           UART23_BASE_ADDR(2,0x04)
#define U2IER           UART23_BASE_ADDR(2,0x04)
#define U2IIR           UART23_BASE_ADDR(2,0x08)
#define U2FCR           UART23_BASE_ADDR(2,0x08)
#define U2LCR           UART23_BASE_ADDR(2,0x0C)
#define U2LSR           UART23_BASE_ADDR(2,0x14)
#define U2SCR           UART23_BASE_ADDR(2,0x1C)
#define U2ACR           UART23_BASE_ADDR(2,0x20)
#define U2ICR           UART23_BASE_ADDR(2,0x24)
#define U2FDR           UART23_BASE_ADDR(2,0x28)
#define U2TER           UART23_BASE_ADDR(2,0x30)
/*------Universal Asynchronous Receiver Transmitter 3 (UART0)-----------------*/
#define U3RBR           UART23_BASE_ADDR(3,0x00)
#define U3THR           UART23_BASE_ADDR(3,0x00)
#define U3DLL           UART23_BASE_ADDR(3,0x00)
#define U3DLM           UART23_BASE_ADDR(3,0x04)
#define U3IER           UART23_BASE_ADDR(3,0x04)
#define U3IIR           UART23_BASE_ADDR(3,0x08)
#define U3FCR           UART23_BASE_ADDR(3,0x08)
#define U3LCR           UART23_BASE_ADDR(3,0x0C)
#define U3LSR           UART23_BASE_ADDR(3,0x14)
#define U3SCR           UART23_BASE_ADDR(3,0x1C)
#define U3ACR           UART23_BASE_ADDR(3,0x20)
#define U3ICR           UART23_BASE_ADDR(3,0x24)
#define U3FDR           UART23_BASE_ADDR(3,0x28)
#define U3TER           UART23_BASE_ADDR(3,0x30)

/*------I2C Interface 0 (I2C0)------------------------------------------------*/
#define I20CONSET       (*(REG32*)(LPC_I2C0_BASE + 0x00))
#define I20STAT         (*(REG32*)(LPC_I2C0_BASE + 0x04))
#define I20DAT          (*(REG32*)(LPC_I2C0_BASE + 0x08))
#define I20ADR          (*(REG32*)(LPC_I2C0_BASE + 0x0C))
#define I20SCLH         (*(REG32*)(LPC_I2C0_BASE + 0x10))
#define I20SCLL         (*(REG32*)(LPC_I2C0_BASE + 0x14))
#define I20CONCLR       (*(REG32*)(LPC_I2C0_BASE + 0x18))
//Slightly different naming
#define I2C0CONSET      I20CONSET
#define I2C0STAT        I20STAT
#define I2C0DAT         I20DAT
#define I2C0ADR         I20ADR
#define I2C0SCLH        I20SCLH
#define I2C0SCLL        I20SCLL
#define I2C0CONCLR      I20CONCLR

/*------I2C Interface 1 (I2C1)------------------------------------------------*/
#define I21CONSET       (*(REG32*)(LPC_I2C1_BASE + 0x00))
#define I21STAT         (*(REG32*)(LPC_I2C1_BASE + 0x04))
#define I21DAT          (*(REG32*)(LPC_I2C1_BASE + 0x08))
#define I21ADR          (*(REG32*)(LPC_I2C1_BASE + 0x0C))
#define I21SCLH         (*(REG32*)(LPC_I2C1_BASE + 0x10))
#define I21SCLL         (*(REG32*)(LPC_I2C1_BASE + 0x14))
#define I21CONCLR       (*(REG32*)(LPC_I2C1_BASE + 0x18))
/*------I2C Interface 2 (I2C2)------------------------------------------------*/
#define I22CONSET       (*(REG32*)(LPC_I2C2_BASE + 0x00))
#define I22STAT         (*(REG32*)(LPC_I2C2_BASE + 0x04))
#define I22DAT          (*(REG32*)(LPC_I2C2_BASE + 0x08))
#define I22ADR          (*(REG32*)(LPC_I2C2_BASE + 0x0C))
#define I22SCLH         (*(REG32*)(LPC_I2C2_BASE + 0x10))
#define I22SCLL         (*(REG32*)(LPC_I2C2_BASE + 0x14))
#define I22CONCLR       (*(REG32*)(LPC_I2C2_BASE + 0x18))
/*------SPI0 (Serial Peripheral Interface 0) ---------------------------------*/
#if i_MCU_MODEL >= 2300
        #ifndef SPI_0_SCK_PIN_NUMBER
                #define SPI_0_SCK_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,15)/**< PINSEL0 Mask for SPI */
        #endif
        #ifndef SPI_0_SEL_PIN_NUMBER
                #define SPI_0_SEL_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 1)
        #endif
        #ifndef SPI_0_MISO_PIN_NUMBER
                #define SPI_0_MISO_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 2)
        #endif
        #ifndef SPI_0_ALL_PIN_SELECT
                #define SPI_0_ALL_PIN_SELECT    3
        #endif
        #ifndef SSP_0_ALL_PIN_SELECT
                #define SSP_0_ALL_PIN_SELECT 2
        #endif
#else /* i_MCU_MODEL >= 2300*/
        #ifndef SPI_0_ALL_PIN_SELECT
                #define SPI_0_ALL_PIN_SELECT    2
        #endif

        #ifndef SPI_0_SCK_PIN_NUMBER
                #define SPI_0_SCK_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,4)
        #endif
        #ifndef SPI_0_MISO_PIN_NUMBER
                #define SPI_0_MISO_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 1)
        #endif
        #ifndef SPI_0_SEL_PIN_NUMBER
                #define SPI_0_SEL_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 3)
        #endif


        #endif
        #ifndef SPI_0_MOSI_PIN_NUMBER
                #define SPI_0_MOSI_PIN_NUMBER (SPI_0_MISO_PIN_NUMBER + 1) /* always after MISO*/
        #endif
#endif


#define S0SPCR          (*(REG32*)(LPC_SPI0_BASE + 0x00))
#define S0SPSR          (*(REG32*)(LPC_SPI0_BASE + 0x04))
#define S0SPDR          (*(REG32*)(LPC_SPI0_BASE + 0x08))
#define S0SPCCR         (*(REG32*)(LPC_SPI0_BASE + 0x0C))
#define S0SPTCR         (*(REG32*)(LPC_SPI0_BASE + 0x10)) //SPI Test Control Register ??
#define S0SPTSR         (*(REG32*)(LPC_SPI0_BASE + 0x14)) //SPI Test Status Register ??
#define S0SPINT         (*(REG32*)(LPC_SPI0_BASE + 0x1C))
/*------ SSP0 Controller-------------------- ---------------------------------*/
#define SSP0CR0         (*(REG32*)(LPC_SSP0_BASE + 0x00))
#define SSP0CR1         (*(REG32*)(LPC_SSP0_BASE + 0x04))
#define SSP0DR          (*(REG32*)(LPC_SSP0_BASE + 0x08))
#define SSP0SR          (*(REG32*)(LPC_SSP0_BASE + 0x0C))
#define SSP0CPSR        (*(REG32*)(LPC_SSP0_BASE + 0x10))
#define SSP0IMSC        (*(REG32*)(LPC_SSP0_BASE + 0x14))
#define SSP0RIS         (*(REG32*)(LPC_SSP0_BASE + 0x18))
#define SSP0MIS         (*(REG32*)(LPC_SSP0_BASE + 0x1C))
#define SSP0ICR         (*(REG32*)(LPC_SSP0_BASE + 0x20))
#define SSP0DMACR       (*(REG32*)(LPC_SSP0_BASE + 0x24))
/*------------------------------------*/
#if i_MCU_MODEL >= 2300
        #ifndef SSP_1_SCK_PIN_NUMBER
                #define SSP_1_SCK_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,7)/**< PINSEL0 Mask for SPI */
        #endif
        #ifndef SSP_1_SEL_PIN_NUMBER
                #define SSP_1_SEL_PIN_NUMBER (SSP_1_SCK_PIN_NUMBER - 1)
        #endif
        #ifndef SSP_1_MISO_PIN_NUMBER
                #define SSP_1_MISO_PIN_NUMBER (SSP_1_SCK_PIN_NUMBER + 1)
        #endif
        #ifndef SSP_1_MOSI_PIN_NUMBER
                #define SSP_1_MOSI_PIN_NUMBER (SSP_1_SCK_PIN_NUMBER + 2)
        #endif
        #ifndef SSP_1_ALL_PIN_SELECT
                #define SSP_1_ALL_PIN_SELECT    2
        #endif
/*------ SSP1 Controller-------------------- ---------------------------------*/
#define SSP1CR0         (*(REG32*)(LPC_SSP1_BASE + 0x00))
#define SSP1CR1         (*(REG32*)(LPC_SSP1_BASE + 0x04))
#define SSP1DR          (*(REG32*)(LPC_SSP1_BASE + 0x08))
#define SSP1SR          (*(REG32*)(LPC_SSP1_BASE + 0x0C))
#define SSP1CPSR        (*(REG32*)(LPC_SSP1_BASE + 0x10))
#define SSP1IMSC        (*(REG32*)(LPC_SSP1_BASE + 0x14))
#define SSP1RIS         (*(REG32*)(LPC_SSP1_BASE + 0x18))
#define SSP1MIS         (*(REG32*)(LPC_SSP1_BASE + 0x1C))
#define SSP1ICR         (*(REG32*)(LPC_SSP1_BASE + 0x20))
#define SSP1DMACR       (*(REG32*)(LPC_SSP1_BASE + 0x24))
#endif /*i_MCU_MODEL*/

/*-------------- Real Time Clock  --------------------------------------------*/
/* ---- RTC: Miscellaneous Register Group ------------------ */
#define RTC_ILR         (*(REG32*)(LPC_RTC_BASE + 0x00))
#define RTC_CTC         (*(REG32*)(LPC_RTC_BASE + 0x04))
#define RTC_CCR         (*(REG32*)(LPC_RTC_BASE + 0x08))
#define RTC_CIIR        (*(REG32*)(LPC_RTC_BASE + 0x0C))
#define RTC_AMR         (*(REG32*)(LPC_RTC_BASE + 0x10))
#define RTC_CTIME0      (*(REG32*)(LPC_RTC_BASE + 0x14))
#define RTC_CTIME1      (*(REG32*)(LPC_RTC_BASE + 0x18))
#define RTC_CTIME2      (*(REG32*)(LPC_RTC_BASE + 0x1C))

/* ---- RTC: Timer Control Group --------------------------- */
#define RTC_SEC         (*(REG32*)(LPC_RTC_BASE + 0x20))
#define RTC_MIN         (*(REG32*)(LPC_RTC_BASE + 0x24))
#define RTC_HOUR        (*(REG32*)(LPC_RTC_BASE + 0x28))
#define RTC_DOM         (*(REG32*)(LPC_RTC_BASE + 0x2C))
#define RTC_DOW         (*(REG32*)(LPC_RTC_BASE + 0x30))
#define RTC_DOY         (*(REG32*)(LPC_RTC_BASE + 0x34))
#define RTC_MONTH       (*(REG32*)(LPC_RTC_BASE + 0x38))
#define RTC_YEAR        (*(REG32*)(LPC_RTC_BASE + 0x3C))
#define RTC_CISS        (*(REG32*)(LPC_RTC_BASE + 0x40))

/* ---- RTC: Alarm Control Group --------------------------- */
#define RTC_ALSEC       (*(REG32*)(LPC_RTC_BASE + 0x60))
#define RTC_ALMIN       (*(REG32*)(LPC_RTC_BASE + 0x64))
#define RTC_ALHOUR      (*(REG32*)(LPC_RTC_BASE + 0x68))
#define RTC_ALDOM       (*(REG32*)(LPC_RTC_BASE + 0x6C))
#define RTC_ALDOW       (*(REG32*)(LPC_RTC_BASE + 0x70))
#define RTC_ALDOY       (*(REG32*)(LPC_RTC_BASE + 0x74))
#define RTC_ALMON       (*(REG32*)(LPC_RTC_BASE + 0x78))
#define RTC_ALYEAR      (*(REG32*)(LPC_RTC_BASE + 0x7C))
/* ---- RTC: Reference Clock Divider Group ----------------- */
#define RTC_PREINT      (*(REG32*)(LPC_RTC_BASE + 0x80))
#define RTC_PREFRAC     (*(REG32*)(LPC_RTC_BASE + 0x84))
/*------------------------ A/D Converter 0 (AD0) -----------------------------*/
#define AD0CR           (*(REG32*)(LPC_AD0_BASE  + 0x00))
#define AD0GDR          (*(REG32*)(LPC_AD0_BASE + 0x04))
#define AD0INTEN        (*(REG32*)(LPC_AD0_BASE + 0x0C))
#define AD0DR0          (*(REG32*)(LPC_AD0_BASE + 0x10))
#define AD0DR1          (*(REG32*)(LPC_AD0_BASE + 0x14))
#define AD0DR2          (*(REG32*)(LPC_AD0_BASE + 0x18))
#define AD0DR3          (*(REG32*)(LPC_AD0_BASE + 0x1C))
#define AD0DR4          (*(REG32*)(LPC_AD0_BASE + 0x20))
#define AD0DR5          (*(REG32*)(LPC_AD0_BASE + 0x24))
#define AD0DR6          (*(REG32*)(LPC_AD0_BASE + 0x28))
#define AD0DR7          (*(REG32*)(LPC_AD0_BASE + 0x2C))
#define AD0STAT         (*(REG32*)(LPC_AD0_BASE + 0x30))


/*-------------------------------- D/A Converter -----------------------------*/
#define DACR            (*(REG32*)(LPC_DAC_BASE + 0x0))
/*-------------------------------- Watchdog-----------------------------*/
#define WDMOD           (*(REG32*)(LPC_WDG_BASE + 0x0))
#define WDTC            (*(REG32*)(LPC_WDG_BASE + 0x04))
#define WDFEED          (*(REG32*)(LPC_WDG_BASE + 0x08))
#define WDTV            (*(REG32*)(LPC_WDG_BASE + 0x0C))
#define WDCLKSEL        (*(REG32*)(LPC_WDG_BASE + 0x10))

/*-------------- Ethernet ----------------------------------------------------*/
#define MAC_MAC1        (*(REG32*)(LPC_MAC_BASE + 0x000)) /* MAC config reg 1 */
#define MAC_MAC2        (*(REG32*)(LPC_MAC_BASE + 0x004)) /* MAC config reg 2 */
#define MAC_IPGT        (*(REG32*)(LPC_MAC_BASE + 0x008)) /* b2b InterPacketGap reg */
#define MAC_IPGR        (*(REG32*)(LPC_MAC_BASE + 0x00C)) /* non b2b InterPacketGap reg */
#define MAC_CLRT        (*(REG32*)(LPC_MAC_BASE + 0x010)) /* CoLlision window/ReTry reg */
#define MAC_MAXF        (*(REG32*)(LPC_MAC_BASE + 0x014)) /* MAXimum Frame reg */
#define MAC_SUPP        (*(REG32*)(LPC_MAC_BASE + 0x018)) /* PHY SUPPort reg */
#define MAC_TEST        (*(REG32*)(LPC_MAC_BASE + 0x01C)) /* TEST reg */
#define MAC_MCFG        (*(REG32*)(LPC_MAC_BASE + 0x020)) /* MII Mgmt ConFiG reg */
#define MAC_MCMD        (*(REG32*)(LPC_MAC_BASE + 0x024)) /* MII Mgmt CoMmanD reg */
#define MAC_MADR        (*(REG32*)(LPC_MAC_BASE + 0x028)) /* MII Mgmt ADdRess reg */
#define MAC_MWTD        (*(REG32*)(LPC_MAC_BASE + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
#define MAC_MRDD        (*(REG32*)(LPC_MAC_BASE + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
#define MAC_MIND        (*(REG32*)(LPC_MAC_BASE + 0x034)) /* MII Mgmt INDicators reg (RO) */

#define MAC_SA0         (*(REG32*)(LPC_MAC_BASE + 0x040)) /* Station Address 0 reg */
#define MAC_SA1         (*(REG32*)(LPC_MAC_BASE + 0x044)) /* Station Address 1 reg */
#define MAC_SA2         (*(REG32*)(LPC_MAC_BASE + 0x048)) /* Station Address 2 reg */

#define MAC_COMMAND             (*(REG32*)(LPC_MAC_BASE + 0x100)) /* Command reg */
#define MAC_STATUS              (*(REG32*)(LPC_MAC_BASE + 0x104)) /* Status reg (RO) */
#define MAC_RXDESCRIPTOR        (*(REG32*)(LPC_MAC_BASE + 0x108)) /* Rx descriptor base address reg */
#define MAC_RXSTATUS            (*(REG32*)(LPC_MAC_BASE + 0x10C)) /* Rx status base address reg */
#define MAC_RXDESCRIPTORNUM     (*(REG32*)(LPC_MAC_BASE + 0x110)) /* Rx number of descriptors reg */
#define MAC_RXPRODUCEINDEX      (*(REG32*)(LPC_MAC_BASE + 0x114)) /* Rx produce index reg (RO) */
#define MAC_RXCONSUMEINDEX      (*(REG32*)(LPC_MAC_BASE + 0x118)) /* Rx consume index reg */
#define MAC_TXDESCRIPTOR        (*(REG32*)(LPC_MAC_BASE + 0x11C)) /* Tx descriptor base address reg */
#define MAC_TXSTATUS            (*(REG32*)(LPC_MAC_BASE + 0x120)) /* Tx status base address reg */
#define MAC_TXDESCRIPTORNUM     (*(REG32*)(LPC_MAC_BASE + 0x124)) /* Tx number of descriptors reg */
#define MAC_TXPRODUCEINDEX      (*(REG32*)(LPC_MAC_BASE + 0x128)) /* Tx produce index reg */
#define MAC_TXCONSUMEINDEX      (*(REG32*)(LPC_MAC_BASE + 0x12C)) /* Tx consume index reg (RO) */

#define MAC_TSV0                (*(REG32*)(LPC_MAC_BASE + 0x158)) /* Tx status vector 0 reg (RO) */
#define MAC_TSV1                (*(REG32*)(LPC_MAC_BASE + 0x15C)) /* Tx status vector 1 reg (RO) */
#define MAC_RSV                 (*(REG32*)(LPC_MAC_BASE + 0x160)) /* Rx status vector reg (RO) */

#define MAC_FLOWCONTROLCNT      (*(REG32*)(LPC_MAC_BASE + 0x170)) /* Flow control counter reg */
#define MAC_FLOWCONTROLSTS      (*(REG32*)(LPC_MAC_BASE + 0x174)) /* Flow control status reg */

#define MAC_RXFILTERCTRL        (*(REG32*)(LPC_MAC_BASE + 0x200)) /* Rx filter ctrl reg */
#define MAC_RXFILTERWOLSTS      (*(REG32*)(LPC_MAC_BASE + 0x204)) /* Rx filter WoL status reg (RO) */
#define MAC_RXFILTERWOLCLR      (*(REG32*)(LPC_MAC_BASE + 0x208)) /* Rx filter WoL clear reg (WO) */

#define MAC_HASHFILTERL         (*(REG32*)(LPC_MAC_BASE + 0x210)) /* Hash filter LSBs reg */
#define MAC_HASHFILTERH         (*(REG32*)(LPC_MAC_BASE + 0x214)) /* Hash filter MSBs reg */

#define MAC_INTSTATUS           (*(REG32*)(LPC_MAC_BASE + 0xFE0)) /* Interrupt status reg (RO) */
#define MAC_INTENABLE           (*(REG32*)(LPC_MAC_BASE + 0xFE4)) /* Interrupt enable reg  */
#define MAC_INTCLEAR            (*(REG32*)(LPC_MAC_BASE + 0xFE8)) /* Interrupt clear reg (WO) */
#define MAC_INTSET              (*(REG32*)(LPC_MAC_BASE + 0xFEC)) /* Interrupt set reg (WO) */

#define MAC_POWERDOWN           (*(REG32*)(LPC_MAC_BASE + 0xFF4)) /* Power-down reg */
#define MAC_MODULEID            (*(REG32*)(LPC_MAC_BASE + 0xFFC)) /* Module ID reg (RO) */



/*--------------  MultiMedia Card Interface(MCI) Controller ------------------*/
#define MCI_POWER      (*(REG8 *)(LPC_MCI_BASE + 0x00))
#define MCI_CLOCK      (*(REG16*)(LPC_MCI_BASE + 0x04))
#define MCI_ARGUMENT   (*(REG32*)(LPC_MCI_BASE + 0x08))
#define MCI_COMMAND    (*(REG16*)(LPC_MCI_BASE + 0x0C))
#define MCI_RESP_CMD   (*(REG8*)(LPC_MCI_BASE + 0x10))
#define MCI_RESP0      (*(REG32*)(LPC_MCI_BASE + 0x14))
#define MCI_RESP1      (*(REG32*)(LPC_MCI_BASE + 0x18))
#define MCI_RESP2      (*(REG32*)(LPC_MCI_BASE + 0x1C))
#define MCI_RESP3      (*(REG32*)(LPC_MCI_BASE + 0x20))
#define MCI_DATA_TMR   (*(REG32*)(LPC_MCI_BASE + 0x24))
#define MCI_DATA_LEN   (*(REG16*)(LPC_MCI_BASE + 0x28))
#define MCI_DATA_CTRL  (*(REG8*)(LPC_MCI_BASE + 0x2C))
#define MCI_DATA_CNT   (*(REG16*)(LPC_MCI_BASE + 0x30))
#define MCI_STATUS     (*(REG32*)(LPC_MCI_BASE + 0x34))
#define MCI_CLEAR      (*(REG16*)(LPC_MCI_BASE + 0x38))
#define MCI_MASK0      (*(REG32*)(LPC_MCI_BASE + 0x3C))
#define MCI_MASK1      (*(REG32*)(LPC_MCI_BASE + 0x40))
#define MCI_FIFO_CNT   (*(REG16*)(LPC_MCI_BASE + 0x48))
#define MCI_FIFO       (*(REG8*)(LPC_MCI_BASE + 0x80))

/*--------------  I2S Interface Controller (I2S)----------- ------------------*/
#define I2S_DAO        (*(REG32*)(LPC_I2S_BASE + 0x00))
#define I2S_DAI        (*(REG32*)(LPC_I2S_BASE + 0x04))
#define I2S_TX_FIFO    (*(REG32*)(LPC_I2S_BASE + 0x08))
#define I2S_RX_FIFO    (*(REG32*)(LPC_I2S_BASE + 0x0C))
#define I2S_STATE      (*(REG32*)(LPC_I2S_BASE + 0x10))
#define I2S_DMA1       (*(REG32*)(LPC_I2S_BASE + 0x14))
#define I2S_DMA2       (*(REG32*)(LPC_I2S_BASE + 0x18))
#define I2S_IRQ        (*(REG32*)(LPC_I2S_BASE + 0x1C))
#define I2S_TXRATE     (*(REG32*)(LPC_I2S_BASE + 0x20))
#define I2S_RXRATE     (*(REG32*)(LPC_I2S_BASE + 0x24))


/*--------------  General-purpose DMA Controller -----------------------------*/
#define GPDMA_INT_STAT         (*(REG32*)(LPC_GPDMA_BASE + 0x000))
#define GPDMA_INT_TCSTAT       (*(REG32*)(LPC_GPDMA_BASE + 0x004))
#define GPDMA_INT_TCCLR        (*(REG32*)(LPC_GPDMA_BASE + 0x008))
#define GPDMA_INT_ERR_STAT     (*(REG32*)(LPC_GPDMA_BASE + 0x00C))
#define GPDMA_INT_ERR_CLR      (*(REG32*)(LPC_GPDMA_BASE + 0x010))
#define GPDMA_RAW_INT_TCSTAT   (*(REG32*)(LPC_GPDMA_BASE + 0x014))
#define GPDMA_RAW_INT_ERR_STAT (*(REG32*)(LPC_GPDMA_BASE + 0x018))
#define GPDMA_ENABLED_CHNS     (*(REG32*)(LPC_GPDMA_BASE + 0x01C))
#define GPDMA_SOFT_BREQ        (*(REG32*)(LPC_GPDMA_BASE + 0x020))
#define GPDMA_SOFT_SREQ        (*(REG32*)(LPC_GPDMA_BASE + 0x024))
#define GPDMA_SOFT_LBREQ       (*(REG32*)(LPC_GPDMA_BASE + 0x028))
#define GPDMA_SOFT_LSREQ       (*(REG32*)(LPC_GPDMA_BASE + 0x02C))
#define GPDMA_CONFIG           (*(REG32*)(LPC_GPDMA_BASE + 0x030))
#define GPDMA_SYNC             (*(REG32*)(LPC_GPDMA_BASE + 0x034))

/*--------------  DMA channel 0 registers ------------------------------------*/
#define GPDMA_CH0_SRC           (*(REG32*)(LPC_GPDMA_BASE + 0x100))
#define GPDMA_CH0_DEST          (*(REG32*)(LPC_GPDMA_BASE + 0x104))
#define GPDMA_CH0_LLI           (*(REG32*)(LPC_GPDMA_BASE + 0x108))
#define GPDMA_CH0_CTRL          (*(REG32*)(LPC_GPDMA_BASE + 0x10C))
#define GPDMA_CH0_CFG           (*(REG32*)(LPC_GPDMA_BASE + 0x110))

/*--------------  DMA channel 1 registers ------------------------------------*/
#define GPDMA_CH1_SRC           (*(REG32*)(LPC_GPDMA_BASE + 0x120))
#define GPDMA_CH1_DEST          (*(REG32*)(LPC_GPDMA_BASE + 0x124))
#define GPDMA_CH1_LLI           (*(REG32*)(LPC_GPDMA_BASE + 0x128))
#define GPDMA_CH1_CTRL          (*(REG32*)(LPC_GPDMA_BASE + 0x12C))
#define GPDMA_CH1_CFG           (*(REG32*)(LPC_GPDMA_BASE + 0x130))
/*----------------------------------------------------------------------------*/
/*--------------  CAN registers ----------------------------------------------*/
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */

#define CAN_AFMR        (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x00))
#define CAN_SFF_SA      (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x04))
#define CAN_SFF_GRP_SA  (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x08))
#define CAN_EFF_SA      (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x0C))
#define CAN_EFF_GRP_SA  (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x10))
#define CAN_EOT         (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x14))
#define CAN_LUT_ERR_ADR (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x18))
#define CAN_LUT_ERR     (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x1C))
#define FCANIE          (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x20))
#define FCANIC0         (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x24))
#define FCANIC1         (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x28))


#define CAN_TX_SR       (*(REG32 *)(LPC_CAN_CENTRAL_BASE + 0x00))
#define CAN_RX_SR       (*(REG32 *)(LPC_CAN_CENTRAL_BASE + 0x04))
#define CAN_MSR         (*(REG32 *)(LPC_CAN_CENTRAL_BASE + 0x08))


#define CAN1MOD         (*(REG32 *)(LPC_CAN1_BASE + 0x00))
#define CAN1CMR         (*(REG32 *)(LPC_CAN1_BASE + 0x04))
#define CAN1GSR         (*(REG32 *)(LPC_CAN1_BASE + 0x08))
#define CAN1ICR         (*(REG32 *)(LPC_CAN1_BASE + 0x0C))
#define CAN1IER         (*(REG32 *)(LPC_CAN1_BASE + 0x10))
#define CAN1BTR         (*(REG32 *)(LPC_CAN1_BASE + 0x14))
#define CAN1EWL         (*(REG32 *)(LPC_CAN1_BASE + 0x18))
#define CAN1SR          (*(REG32 *)(LPC_CAN1_BASE + 0x1C))
#define CAN1RFS         (*(REG32 *)(LPC_CAN1_BASE + 0x20))
#define CAN1RID         (*(REG32 *)(LPC_CAN1_BASE + 0x24))
#define CAN1RDA         (*(REG32 *)(LPC_CAN1_BASE + 0x28))
#define CAN1RDB         (*(REG32 *)(LPC_CAN1_BASE + 0x2C))

#define CAN1TFI1        (*(REG32 *)(LPC_CAN1_BASE + 0x30))
#define CAN1TID1        (*(REG32 *)(LPC_CAN1_BASE + 0x34))
#define CAN1TDA1        (*(REG32 *)(LPC_CAN1_BASE + 0x38))
#define CAN1TDB1        (*(REG32 *)(LPC_CAN1_BASE + 0x3C))
#define CAN1TFI2        (*(REG32 *)(LPC_CAN1_BASE + 0x40))
#define CAN1TID2        (*(REG32 *)(LPC_CAN1_BASE + 0x44))
#define CAN1TDA2        (*(REG32 *)(LPC_CAN1_BASE + 0x48))
#define CAN1TDB2        (*(REG32 *)(LPC_CAN1_BASE + 0x4C))
#define CAN1TFI3        (*(REG32 *)(LPC_CAN1_BASE + 0x50))
#define CAN1TID3        (*(REG32 *)(LPC_CAN1_BASE + 0x54))
#define CAN1TDA3        (*(REG32 *)(LPC_CAN1_BASE + 0x58))
#define CAN1TDB3        (*(REG32 *)(LPC_CAN1_BASE + 0x5C))

#define CAN2MOD         (*(REG32 *)(LPC_CAN2_BASE + 0x00))
#define CAN2CMR         (*(REG32 *)(LPC_CAN2_BASE + 0x04))
#define CAN2GSR         (*(REG32 *)(LPC_CAN2_BASE + 0x08))
#define CAN2ICR         (*(REG32 *)(LPC_CAN2_BASE + 0x0C))
#define CAN2IER         (*(REG32 *)(LPC_CAN2_BASE + 0x10))
#define CAN2BTR         (*(REG32 *)(LPC_CAN2_BASE + 0x14))
#define CAN2EWL         (*(REG32 *)(LPC_CAN2_BASE + 0x18))
#define CAN2SR          (*(REG32 *)(LPC_CAN2_BASE + 0x1C))
#define CAN2RFS         (*(REG32 *)(LPC_CAN2_BASE + 0x20))
#define CAN2RID         (*(REG32 *)(LPC_CAN2_BASE + 0x24))
#define CAN2RDA         (*(REG32 *)(LPC_CAN2_BASE + 0x28))
#define CAN2RDB         (*(REG32 *)(LPC_CAN2_BASE + 0x2C))

#define CAN2TFI1        (*(REG32 *)(LPC_CAN2_BASE + 0x30))
#define CAN2TID1        (*(REG32 *)(LPC_CAN2_BASE + 0x34))
#define CAN2TDA1        (*(REG32 *)(LPC_CAN2_BASE + 0x38))
#define CAN2TDB1        (*(REG32 *)(LPC_CAN2_BASE + 0x3C))
#define CAN2TFI2        (*(REG32 *)(LPC_CAN2_BASE + 0x40))
#define CAN2TID2        (*(REG32 *)(LPC_CAN2_BASE + 0x44))
#define CAN2TDA2        (*(REG32 *)(LPC_CAN2_BASE + 0x48))
#define CAN2TDB2        (*(REG32 *)(LPC_CAN2_BASE + 0x4C))
#define CAN2TFI3        (*(REG32 *)(LPC_CAN2_BASE + 0x50))
#define CAN2TID3        (*(REG32 *)(LPC_CAN2_BASE + 0x54))
#define CAN2TDA3        (*(REG32 *)(LPC_CAN2_BASE + 0x58))
#define CAN2TDB3        (*(REG32 *)(LPC_CAN2_BASE + 0x5C))

/*----------------------------------------------------------------------------*/
/*---------------  USB -------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/*---------------- USB Controller --------------------------------------------*/
#define USB_INT_BASE    0xE01FC1C0
//#define USB_BASE              0xFFE0C200              /* USB Base Address */

#define USB_INT_STAT    (*(REG32*)(USB_INT_BASE + 0x00))


/*------ USB Device Interrupt Registers --------------------- */
#define DEV_INT_STAT    (*(REG32*)(USB_BASE + 0x00))
#define DEV_INT_EN      (*(REG32*)(USB_BASE + 0x04))
#define DEV_INT_CLR     (*(REG32*)(USB_BASE + 0x08))
#define DEV_INT_SET     (*(REG32*)(USB_BASE + 0x0C))
#define DEV_INT_PRIO    (*(REG32*)(USB_BASE + 0x2C))


/*------ USB Device Endpoint Interrupt Registers ------------- */
#define EP_INT_STAT     (*(REG32*)(USB_BASE + 0x30))
#define EP_INT_EN       (*(REG32*)(USB_BASE + 0x34))
#define EP_INT_CLR      (*(REG32*)(USB_BASE + 0x38))
#define EP_INT_SET      (*(REG32*)(USB_BASE + 0x3C))
#define EP_INT_PRIO     (*(REG32*)(USB_BASE + 0x40))


/*------  USB Device Endpoint Realization Registers ---------- */
#define REALIZE_EP      (*(REG32*)(USB_BASE + 0x44))
#define EP_INDEX        (*(REG32*)(USB_BASE + 0x48))
#define MAXPACKET_SIZE  (*(REG32*)(USB_BASE + 0x4C))


/*------  USB Device Command Reagisters ---------------------- */
#define CMD_CODE        (*(REG32*)(USB_BASE + 0x10))
#define CMD_DATA        (*(REG32*)(USB_BASE + 0x14))


/*------  USB Device Data Transfer Registers ----------------- */
#define RX_DATA         (*(REG32*)(USB_BASE + 0x18))
#define TX_DATA         (*(REG32*)(USB_BASE + 0x1C))
#define RX_PLENGTH      (*(REG32*)(USB_BASE + 0x20))
#define TX_PLENGTH      (*(REG32*)(USB_BASE + 0x24))
#define USB_CTRL        (*(REG32*)(USB_BASE + 0x28))

/*------------------------ USB Device DMA Registers -----------*/
#define DMA_REQ_STAT        (*(REG32*)(USB_BASE + 0x50))
#define DMA_REQ_CLR         (*(REG32*)(USB_BASE + 0x54))
#define DMA_REQ_SET         (*(REG32*)(USB_BASE + 0x58))
#define UDCA_HEAD           (*(REG32*)(USB_BASE + 0x80))
#define EP_DMA_STAT         (*(REG32*)(USB_BASE + 0x84))
#define EP_DMA_EN           (*(REG32*)(USB_BASE + 0x88))
#define EP_DMA_DIS          (*(REG32*)(USB_BASE + 0x8C))
#define DMA_INT_STAT        (*(REG32*)(USB_BASE + 0x90))
#define DMA_INT_EN          (*(REG32*)(USB_BASE + 0x94))
#define EOT_INT_STAT        (*(REG32*)(USB_BASE + 0xA0))
#define EOT_INT_CLR         (*(REG32*)(USB_BASE + 0xA4))
#define EOT_INT_SET         (*(REG32*)(USB_BASE + 0xA8))
#define NDD_REQ_INT_STAT    (*(REG32*)(USB_BASE + 0xAC))
#define NDD_REQ_INT_CLR     (*(REG32*)(USB_BASE + 0xB0))
#define NDD_REQ_INT_SET     (*(REG32*)(USB_BASE + 0xB4))
#define SYS_ERR_INT_STAT    (*(REG32*)(USB_BASE + 0xB8))
#define SYS_ERR_INT_CLR     (*(REG32*)(USB_BASE + 0xBC))
#define SYS_ERR_INT_SET     (*(REG32*)(USB_BASE + 0xC0))

/* USB Host and OTG registers are for LPC24xx only */
/*------------------------ USB Host Controller -------------------------------*/
#define HC_REVISION         (*(REG32*)(LPC_USBHC_BASE + 0x00))
#define HC_CONTROL          (*(REG32*)(LPC_USBHC_BASE + 0x04))
#define HC_CMD_STAT         (*(REG32*)(LPC_USBHC_BASE + 0x08))
#define HC_INT_STAT         (*(REG32*)(LPC_USBHC_BASE + 0x0C))
#define HC_INT_EN           (*(REG32*)(LPC_USBHC_BASE + 0x10))
#define HC_INT_DIS          (*(REG32*)(LPC_USBHC_BASE + 0x14))
#define HC_HCCA             (*(REG32*)(LPC_USBHC_BASE + 0x18))
#define HC_PERIOD_CUR_ED    (*(REG32*)(LPC_USBHC_BASE + 0x1C))
#define HC_CTRL_HEAD_ED     (*(REG32*)(LPC_USBHC_BASE + 0x20))
#define HC_CTRL_CUR_ED      (*(REG32*)(LPC_USBHC_BASE + 0x24))
#define HC_BULK_HEAD_ED     (*(REG32*)(LPC_USBHC_BASE + 0x28))
#define HC_BULK_CUR_ED      (*(REG32*)(LPC_USBHC_BASE + 0x2C))
#define HC_DONE_HEAD        (*(REG32*)(LPC_USBHC_BASE + 0x30))
#define HC_FM_INTERVAL      (*(REG32*)(LPC_USBHC_BASE + 0x34))
#define HC_FM_REMAINING     (*(REG32*)(LPC_USBHC_BASE + 0x38))
#define HC_FM_NUMBER        (*(REG32*)(LPC_USBHC_BASE + 0x3C))
#define HC_PERIOD_START     (*(REG32*)(LPC_USBHC_BASE + 0x40))
#define HC_LS_THRHLD        (*(REG32*)(LPC_USBHC_BASE + 0x44))
#define HC_RH_DESCA         (*(REG32*)(LPC_USBHC_BASE + 0x48))
#define HC_RH_DESCB         (*(REG32*)(LPC_USBHC_BASE + 0x4C))
#define HC_RH_STAT          (*(REG32*)(LPC_USBHC_BASE + 0x50))
#define HC_RH_PORT_STAT1    (*(REG32*)(LPC_USBHC_BASE + 0x54))
#define HC_RH_PORT_STAT2    (*(REG32*)(LPC_USBHC_BASE + 0x58))
/*------------------------ USB OTG Controller -------------------------------*/
#define OTG_INT_STAT        (*(REG32*)(LPC_USBOTG_BASE + 0x00))
#define OTG_INT_EN          (*(REG32*)(LPC_USBOTG_BASE + 0x04))
#define OTG_INT_SET         (*(REG32*)(LPC_USBOTG_BASE + 0x08))
#define OTG_INT_CLR         (*(REG32*)(LPC_USBOTG_BASE + 0x0C))
/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
#define OTG_STAT_CTRL       (*(REG32*)(LPC_USBOTG_BASE + 0x10))
#define OTG_TIMER           (*(REG32*)(LPC_USBOTG_BASE + 0x14))

#define OTG_I2C_RX          (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x00))
#define OTG_I2C_TX          (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x00))
#define OTG_I2C_STS         (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x04))
#define OTG_I2C_CTL         (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x08))
#define OTG_I2C_CLKHI       (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x0C))
#define OTG_I2C_CLKLO       (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x10))

/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
#define OTG_CLK_CTRL        (*(REG32*)(LPC_USBOTG_CLK_BASE + 0x04))
#define OTG_CLK_STAT        (*(REG32*)(LPC_USBOTG_CLK_BASE + 0x08))

/* Note: below three register name convention is for LPC23xx USB device only, match
with the spec. update in USB Device Section. */
#define USBPortSel          (*(REG32*)(LPC_USBOTG_BASE + 0x10))
#define USBClkCtrl          (*(REG32*)(LPC_USBOTG_CLK_BASE + 0x04))
#define USBClkSt            (*(REG32*)(LPC_USBOTG_CLK_BASE + 0x08))

/*------------------------ External Memory Controller (EMC) LPC 22xx----------*/
#if ((i_MCU_MODEL >= 2210) && (i_MCU_MODEL < 2299))
        // external memory controller (EMC)
        #define EMC_BCFG0       (*(REG32 (0xFFE00000)))
        #define EMC_BCFG1       (*(REG32 (0xFFE00004)))
        #define EMC_BCFG2       (*(REG32 (0xFFE00008)))
        #define EMC_BCFG3       (*(REG32 (0xFFE0000C)))
#endif
/*------------------------ External Memory Controller (EMC) ------------------*/
#define EMC_CTRL       (*(REG32 *)(LPC_EMC_BASE + 0x000))
#define EMC_STAT       (*(REG32 *)(LPC_EMC_BASE + 0x004))
#define EMC_CONFIG     (*(REG32 *)(LPC_EMC_BASE + 0x008))

/*------------------------ Dynamic RAM access registers  ---------------------*/
#define EMC_DYN_CTRL     (*(REG32 *)(LPC_EMC_BASE + 0x020))
#define EMC_DYN_RFSH     (*(REG32 *)(LPC_EMC_BASE + 0x024))
#define EMC_DYN_RD_CFG   (*(REG32 *)(LPC_EMC_BASE + 0x028))
#define EMC_DYN_RP       (*(REG32 *)(LPC_EMC_BASE + 0x030))
#define EMC_DYN_RAS      (*(REG32 *)(LPC_EMC_BASE + 0x034))
#define EMC_DYN_SREX     (*(REG32 *)(LPC_EMC_BASE + 0x038))
#define EMC_DYN_APR      (*(REG32 *)(LPC_EMC_BASE + 0x03C))
#define EMC_DYN_DAL      (*(REG32 *)(LPC_EMC_BASE + 0x040))
#define EMC_DYN_WR       (*(REG32 *)(LPC_EMC_BASE + 0x044))
#define EMC_DYN_RC       (*(REG32 *)(LPC_EMC_BASE + 0x048))
#define EMC_DYN_RFC      (*(REG32 *)(LPC_EMC_BASE + 0x04C))
#define EMC_DYN_XSR      (*(REG32 *)(LPC_EMC_BASE + 0x050))
#define EMC_DYN_RRD      (*(REG32 *)(LPC_EMC_BASE + 0x054))
#define EMC_DYN_MRD      (*(REG32 *)(LPC_EMC_BASE + 0x058))

#define EMC_DYN_CFG0     (*(REG32 *)(LPC_EMC_BASE + 0x100))
#define EMC_DYN_RASCAS0  (*(REG32 *)(LPC_EMC_BASE + 0x104))
#define EMC_DYN_CFG1     (*(REG32 *)(LPC_EMC_BASE + 0x140))
#define EMC_DYN_RASCAS1  (*(REG32 *)(LPC_EMC_BASE + 0x144))
#define EMC_DYN_CFG2     (*(REG32 *)(LPC_EMC_BASE + 0x160))
#define EMC_DYN_RASCAS2  (*(REG32 *)(LPC_EMC_BASE + 0x164))
#define EMC_DYN_CFG3     (*(REG32 *)(LPC_EMC_BASE + 0x180))
#define EMC_DYN_RASCAS3  (*(REG32 *)(LPC_EMC_BASE + 0x184))
/*------ ТИПЫ ДАННЫХ - DATA TYPES --------------------------------------------*/
/*------ СПИСОК ГЛОБАЛЬНЫХ ФУНЦИЙ - PUBLIC LIST API --------------------------*/
/** @} end of group reg_addresses_LPC2000_old */
/** @} end of group xgportARM7_NXP */

#endif  /* _ARCH_ARM_NXP_LPC2XXX_H_ */