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core_sc000.h
См. документацию.
1 /**************************************************************************//**
2  * @file core_sc000.h
3  * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4  * @version V3.01
5  * @date 22. March 2012
6  *
7  * @note
8  * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9  *
10  * @par
11  * ARM Limited (ARM) is supplying this software for use with Cortex-M
12  * processor based microcontrollers. This file can be freely distributed
13  * within development tools that are supporting such ARM based processors.
14  *
15  * @par
16  * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21  *
22  ******************************************************************************/
23 #if defined ( __ICCARM__ )
24  #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 #ifndef __CORE_SC000_H_GENERIC
32 #define __CORE_SC000_H_GENERIC
33 
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35  CMSIS violates the following MISRA-C:2004 rules:
36 
37  \li Required Rule 8.5, object/function definition in header file.<br>
38  Function definitions in header files are used to allow 'inlining'.
39 
40  \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41  Unions are used for effective representation of core registers.
42 
43  \li Advisory Rule 19.7, Function-like macro defined.<br>
44  Function-like macros are used to allow more efficient code.
45  */
46 
47 
48 /*******************************************************************************
49  * CMSIS definitions
50  ******************************************************************************/
51 /** \ingroup SC000
52  @{
53  */
54 
55 /* CMSIS SC000 definitions */
56 #define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __SC000_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
58 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
59  __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
60 
61 #define __CORTEX_SC (0) /*!< Cortex secure core */
62 
63 
64 #if defined ( __CC_ARM )
65  #define __ASM __asm /*!< asm keyword for ARM Compiler */
66  #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67  #define __STATIC_INLINE static __inline
68 
69 #elif defined ( __ICCARM__ )
70  #define __ASM __asm /*!< asm keyword for IAR Compiler */
71  #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72  #define __STATIC_INLINE static inline
73 
74 #elif defined ( __GNUC__ )
75  #define __ASM __asm /*!< asm keyword for GNU Compiler */
76  #define __INLINE inline /*!< inline keyword for GNU Compiler */
77  #define __STATIC_INLINE static inline
78 
79 #elif defined ( __TASKING__ )
80  #define __ASM __asm /*!< asm keyword for TASKING Compiler */
81  #define __INLINE inline /*!< inline keyword for TASKING Compiler */
82  #define __STATIC_INLINE static inline
83 
84 #endif
85 
86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
87 */
88 #define __FPU_USED 0
89 
90 #if defined ( __CC_ARM )
91  #if defined __TARGET_FPU_VFP
92  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93  #endif
94 
95 #elif defined ( __ICCARM__ )
96  #if defined __ARMVFP__
97  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98  #endif
99 
100 #elif defined ( __GNUC__ )
101  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103  #endif
104 
105 #elif defined ( __TASKING__ )
106  #if defined __FPU_VFP__
107  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108  #endif
109 #endif
110 
111 #include <stdint.h> /* standard types definitions */
112 #include <core_cmInstr.h> /* Core Instruction Access */
113 #include <core_cmFunc.h> /* Core Function Access */
114 
115 #endif /* __CORE_SC000_H_GENERIC */
116 
117 #ifndef __CMSIS_GENERIC
118 
119 #ifndef __CORE_SC000_H_DEPENDANT
120 #define __CORE_SC000_H_DEPENDANT
121 
122 /* check device defines and use defaults */
123 #if defined __CHECK_DEVICE_DEFINES
124  #ifndef __SC000_REV
125  #define __SC000_REV 0x0000
126  #warning "__SC000_REV not defined in device header file; using default!"
127  #endif
128 
129  #ifndef __MPU_PRESENT
130  #define __MPU_PRESENT 0
131  #warning "__MPU_PRESENT not defined in device header file; using default!"
132  #endif
133 
134  #ifndef __NVIC_PRIO_BITS
135  #define __NVIC_PRIO_BITS 2
136  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
137  #endif
138 
139  #ifndef __Vendor_SysTickConfig
140  #define __Vendor_SysTickConfig 0
141  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
142  #endif
143 #endif
144 
145 /* IO definitions (access restrictions to peripheral registers) */
146 /**
147  \defgroup CMSIS_glob_defs CMSIS Global Defines
148 
149  <strong>IO Type Qualifiers</strong> are used
150  \li to specify the access to peripheral variables.
151  \li for automatic generation of peripheral register debug information.
152 */
153 #ifdef __cplusplus
154  #define __I volatile /*!< Defines 'read only' permissions */
155 #else
156  #define __I volatile const /*!< Defines 'read only' permissions */
157 #endif
158 #define __O volatile /*!< Defines 'write only' permissions */
159 #define __IO volatile /*!< Defines 'read / write' permissions */
160 
161 /*@} end of group SC000 */
162 
163 
164 
165 /*******************************************************************************
166  * Register Abstraction
167  Core Register contain:
168  - Core Register
169  - Core NVIC Register
170  - Core SCB Register
171  - Core SysTick Register
172  - Core MPU Register
173  ******************************************************************************/
174 /** \defgroup CMSIS_core_register Defines and Type Definitions
175  \brief Type definitions and defines for Cortex-M processor based devices.
176 */
177 
178 /** \ingroup CMSIS_core_register
179  \defgroup CMSIS_CORE Status and Control Registers
180  \brief Core Register type definitions.
181  @{
182  */
183 
184 /** \brief Union type to access the Application Program Status Register (APSR).
185  */
186 typedef union
187 {
188  struct
189  {
190 #if (__CORTEX_M != 0x04)
191  uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
192 #else
193  uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
194  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
195  uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
196 #endif
197  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
198  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
199  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
200  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
201  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
202  } b; /*!< Structure used for bit access */
203  uint32_t w; /*!< Type used for word access */
204 } APSR_Type;
205 
206 
207 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
208  */
209 typedef union
210 {
211  struct
212  {
213  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
214  uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
215  } b; /*!< Structure used for bit access */
216  uint32_t w; /*!< Type used for word access */
217 } IPSR_Type;
218 
219 
220 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
221  */
222 typedef union
223 {
224  struct
225  {
226  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
227 #if (__CORTEX_M != 0x04)
228  uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
229 #else
230  uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
231  uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
232  uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
233 #endif
234  uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
235  uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
236  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
237  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
238  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
239  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
240  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
241  } b; /*!< Structure used for bit access */
242  uint32_t w; /*!< Type used for word access */
243 } xPSR_Type;
244 
245 
246 /** \brief Union type to access the Control Registers (CONTROL).
247  */
248 typedef union
249 {
250  struct
251  {
252  uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
253  uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
254  uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
255  uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
256  } b; /*!< Structure used for bit access */
257  uint32_t w; /*!< Type used for word access */
258 } CONTROL_Type;
259 
260 /*@} end of group CMSIS_CORE */
261 
262 
263 /** \ingroup CMSIS_core_register
264  \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
265  \brief Type definitions for the NVIC Registers
266  @{
267  */
268 
269 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
270  */
271 typedef struct
272 {
273  __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
274  uint32_t RESERVED0[31];
275  __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
276  uint32_t RSERVED1[31];
277  __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
278  uint32_t RESERVED2[31];
279  __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
280  uint32_t RESERVED3[31];
281  uint32_t RESERVED4[64];
282  __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
283 } NVIC_Type;
284 
285 /*@} end of group CMSIS_NVIC */
286 
287 
288 /** \ingroup CMSIS_core_register
289  \defgroup CMSIS_SCB System Control Block (SCB)
290  \brief Type definitions for the System Control Block Registers
291  @{
292  */
293 
294 /** \brief Structure type to access the System Control Block (SCB).
295  */
296 typedef struct
297 {
298  __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
299  __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
300  __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
301  __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
302  __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
303  __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
304  uint32_t RESERVED0[1];
305  __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
306  __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
307  uint32_t RESERVED1[154];
308  __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
309 } SCB_Type;
310 
311 /* SCB CPUID Register Definitions */
312 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
313 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
314 
315 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
316 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
317 
318 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
319 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
320 
321 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
322 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
323 
324 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
325 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
326 
327 /* SCB Interrupt Control State Register Definitions */
328 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
329 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
330 
331 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
332 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
333 
334 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
335 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
336 
337 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
338 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
339 
340 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
341 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
342 
343 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
344 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
345 
346 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
347 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
348 
349 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
350 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
351 
352 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
353 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
354 
355 /* SCB Interrupt Control State Register Definitions */
356 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
357 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
358 
359 /* SCB Application Interrupt and Reset Control Register Definitions */
360 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
361 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
362 
363 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
364 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
365 
366 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
367 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
368 
369 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
370 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
371 
372 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
373 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
374 
375 /* SCB System Control Register Definitions */
376 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
377 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
378 
379 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
380 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
381 
382 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
383 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
384 
385 /* SCB Configuration Control Register Definitions */
386 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
387 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
388 
389 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
390 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
391 
392 /* SCB System Handler Control and State Register Definitions */
393 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
394 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
395 
396 /* SCB Security Features Register Definitions */
397 #define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
398 #define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
399 
400 #define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
401 #define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
402 
403 /*@} end of group CMSIS_SCB */
404 
405 
406 /** \ingroup CMSIS_core_register
407  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
408  \brief Type definitions for the System Control and ID Register not in the SCB
409  @{
410  */
411 
412 /** \brief Structure type to access the System Control and ID Register not in the SCB.
413  */
414 typedef struct
415 {
416  uint32_t RESERVED0[2];
417  __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
418 } SCnSCB_Type;
419 
420 /* Auxiliary Control Register Definitions */
421 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
422 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
423 
424 /*@} end of group CMSIS_SCnotSCB */
425 
426 
427 /** \ingroup CMSIS_core_register
428  \defgroup CMSIS_SysTick System Tick Timer (SysTick)
429  \brief Type definitions for the System Timer Registers.
430  @{
431  */
432 
433 /** \brief Structure type to access the System Timer (SysTick).
434  */
435 typedef struct
436 {
437  __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
438  __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
439  __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
440  __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
441 } SysTick_Type;
442 
443 /* SysTick Control / Status Register Definitions */
444 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
445 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
446 
447 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
448 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
449 
450 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
451 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
452 
453 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
454 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
455 
456 /* SysTick Reload Register Definitions */
457 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
458 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
459 
460 /* SysTick Current Register Definitions */
461 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
462 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
463 
464 /* SysTick Calibration Register Definitions */
465 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
466 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
467 
468 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
469 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
470 
471 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
472 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
473 
474 /*@} end of group CMSIS_SysTick */
475 
476 #if (__MPU_PRESENT == 1)
477 /** \ingroup CMSIS_core_register
478  \defgroup CMSIS_MPU Memory Protection Unit (MPU)
479  \brief Type definitions for the Memory Protection Unit (MPU)
480  @{
481  */
482 
483 /** \brief Structure type to access the Memory Protection Unit (MPU).
484  */
485 typedef struct
486 {
487  __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
488  __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
489  __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
490  __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
491  __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
492 } MPU_Type;
493 
494 /* MPU Type Register */
495 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
496 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
497 
498 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
499 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
500 
501 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
502 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
503 
504 /* MPU Control Register */
505 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
506 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
507 
508 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
509 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
510 
511 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
512 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
513 
514 /* MPU Region Number Register */
515 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
516 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
517 
518 /* MPU Region Base Address Register */
519 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
520 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
521 
522 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
523 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
524 
525 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
526 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
527 
528 /* MPU Region Attribute and Size Register */
529 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
530 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
531 
532 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
533 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
534 
535 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
536 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
537 
538 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
539 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
540 
541 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
542 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
543 
544 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
545 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
546 
547 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
548 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
549 
550 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
551 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
552 
553 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
554 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
555 
556 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
557 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
558 
559 /*@} end of group CMSIS_MPU */
560 #endif
561 
562 
563 /** \ingroup CMSIS_core_register
564  \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
565  \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
566  are only accessible over DAP and not via processor. Therefore
567  they are not covered by the Cortex-M0 header file.
568  @{
569  */
570 /*@} end of group CMSIS_CoreDebug */
571 
572 
573 /** \ingroup CMSIS_core_register
574  \defgroup CMSIS_core_base Core Definitions
575  \brief Definitions for base addresses, unions, and structures.
576  @{
577  */
578 
579 /* Memory mapping of SC000 Hardware */
580 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
581 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
582 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
583 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
584 
585 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
586 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
587 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
588 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
589 
590 #if (__MPU_PRESENT == 1)
591  #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
592  #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
593 #endif
594 
595 /*@} */
596 
597 
598 
599 /*******************************************************************************
600  * Hardware Abstraction Layer
601  Core Function Interface contains:
602  - Core NVIC Functions
603  - Core SysTick Functions
604  - Core Register Access Functions
605  ******************************************************************************/
606 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
607 */
608 
609 
610 
611 /* ########################## NVIC functions #################################### */
612 /** \ingroup CMSIS_Core_FunctionInterface
613  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
614  \brief Functions that manage interrupts and exceptions via the NVIC.
615  @{
616  */
617 
618 /* Interrupt Priorities are WORD accessible only under ARMv6M */
619 /* The following MACROS handle generation of the register offset and byte masks */
620 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
621 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
622 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
623 
624 
625 /** \brief Enable External Interrupt
626 
627  The function enables a device-specific interrupt in the NVIC interrupt controller.
628 
629  \param [in] IRQn External interrupt number. Value cannot be negative.
630  */
631 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
632 {
633  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
634 }
635 
636 
637 /** \brief Disable External Interrupt
638 
639  The function disables a device-specific interrupt in the NVIC interrupt controller.
640 
641  \param [in] IRQn External interrupt number. Value cannot be negative.
642  */
643 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
644 {
645  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
646 }
647 
648 
649 /** \brief Get Pending Interrupt
650 
651  The function reads the pending register in the NVIC and returns the pending bit
652  for the specified interrupt.
653 
654  \param [in] IRQn Interrupt number.
655 
656  \return 0 Interrupt status is not pending.
657  \return 1 Interrupt status is pending.
658  */
659 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
660 {
661  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
662 }
663 
664 
665 /** \brief Set Pending Interrupt
666 
667  The function sets the pending bit of an external interrupt.
668 
669  \param [in] IRQn Interrupt number. Value cannot be negative.
670  */
671 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
672 {
673  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
674 }
675 
676 
677 /** \brief Clear Pending Interrupt
678 
679  The function clears the pending bit of an external interrupt.
680 
681  \param [in] IRQn External interrupt number. Value cannot be negative.
682  */
683 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
684 {
685  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
686 }
687 
688 
689 /** \brief Set Interrupt Priority
690 
691  The function sets the priority of an interrupt.
692 
693  \note The priority cannot be set for every core interrupt.
694 
695  \param [in] IRQn Interrupt number.
696  \param [in] priority Priority to set.
697  */
698 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
699 {
700  if(IRQn < 0) {
701  SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
702  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
703  else {
704  NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
705  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
706 }
707 
708 
709 /** \brief Get Interrupt Priority
710 
711  The function reads the priority of an interrupt. The interrupt
712  number can be positive to specify an external (device specific)
713  interrupt, or negative to specify an internal (core) interrupt.
714 
715 
716  \param [in] IRQn Interrupt number.
717  \return Interrupt Priority. Value is aligned automatically to the implemented
718  priority bits of the microcontroller.
719  */
720 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
721 {
722 
723  if(IRQn < 0) {
724  return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for SC000 system interrupts */
725  else {
726  return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
727 }
728 
729 
730 /** \brief System Reset
731 
732  The function initiates a system reset request to reset the MCU.
733  */
734 __STATIC_INLINE void NVIC_SystemReset(void)
735 {
736  __DSB(); /* Ensure all outstanding memory accesses included
737  buffered write are completed before reset */
738  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
739  SCB_AIRCR_SYSRESETREQ_Msk);
740  __DSB(); /* Ensure completion of memory access */
741  while(1); /* wait until reset */
742 }
743 
744 /*@} end of CMSIS_Core_NVICFunctions */
745 
746 
747 
748 /* ################################## SysTick function ############################################ */
749 /** \ingroup CMSIS_Core_FunctionInterface
750  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
751  \brief Functions that configure the System.
752  @{
753  */
754 
755 #if (__Vendor_SysTickConfig == 0)
756 
757 /** \brief System Tick Configuration
758 
759  The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
760  Counter is in free running mode to generate periodic interrupts.
761 
762  \param [in] ticks Number of ticks between two interrupts.
763 
764  \return 0 Function succeeded.
765  \return 1 Function failed.
766 
767  \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
768  function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
769  must contain a vendor-specific implementation of this function.
770 
771  */
772 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
773 {
774  if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
775 
776  SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
777  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
778  SysTick->VAL = 0; /* Load the SysTick Counter Value */
779  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
780  SysTick_CTRL_TICKINT_Msk |
781  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
782  return (0); /* Function successful */
783 }
784 
785 #endif
786 
787 /*@} end of CMSIS_Core_SysTickFunctions */
788 
789 
790 
791 
792 #endif /* __CORE_SC000_H_DEPENDANT */
793 
794 #endif /* __CMSIS_GENERIC */
795 
796 #ifdef __cplusplus
797 }
798 #endif