CMSIS2000  0.0.7
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LPC17xx_System
Collaboration diagram for LPC17xx_System:

Modules

 LPC17xx System Defines
 LPC17xx System Public Variables
 LPC17xx System Public Functions

Data Structures

struct  LPC_ADC_TypeDef
 Analog-to-Digital Converter (ADC) register structure definition. More...
struct  LPC_CAN_TypeDef
 Controller Area Network Controller (CAN) register structure definition. More...
struct  LPC_CANAF_RAM_TypeDef
 Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition. More...
struct  LPC_CANAF_TypeDef
 Controller Area Network Acceptance Filter(CANAF) register structure definition. More...
struct  LPC_CANCR_TypeDef
 Controller Area Network Central (CANCR) register structure definition. More...
struct  LPC_DAC_TypeDef
 Digital-to-Analog Converter (DAC) register structure definition. More...
struct  LPC_EMAC_TypeDef
 Ethernet Media Access Controller (EMAC) register structure definition. More...
struct  LPC_GPDMA_TypeDef
 General Purpose Direct Memory Access (GPDMA) register structure definition. More...
struct  LPC_GPDMACH_TypeDef
 General Purpose Direct Memory Access Channel (GPDMACH) register structure definition. More...
struct  LPC_GPIO_TypeDef
 General Purpose Input/Output (GPIO) register structure definition. More...
struct  LPC_GPIOINT_TypeDef
 General Purpose Input/Output interrupt (GPIOINT) register structure definition. More...
struct  LPC_I2C_TypeDef
 Inter-Integrated Circuit (I2C) register structure definition. More...
struct  LPC_I2S_TypeDef
 Inter IC Sound (I2S) register structure definition. More...
struct  LPC_MCPWM_TypeDef
 Motor Control Pulse-Width Modulation (MCPWM) register structure definition. More...
struct  LPC_PINCON_TypeDef
 Pin Connect Block (PINCON) register structure definition. More...
struct  LPC_PWM_TypeDef
 Pulse-Width Modulation (PWM) register structure definition. More...
struct  LPC_QEI_TypeDef
 Quadrature Encoder Interface (QEI) register structure definition. More...
struct  LPC_RIT_TypeDef
 Repetitive Interrupt Timer (RIT) register structure definition. More...
struct  LPC_RTC_TypeDef
 Real-Time Clock (RTC) register structure definition. More...
struct  LPC_SC_TypeDef
 System Control (SC) register structure definition. More...
struct  LPC_SPI_TypeDef
 Serial Peripheral Interface (SPI) register structure definition. More...
struct  LPC_SSP_TypeDef
 Synchronous Serial Communication (SSP) register structure definition. More...
struct  LPC_TIM_TypeDef
 Timer (TIM) register structure definition. More...
struct  LPC_UART0_TypeDef
 Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition. More...
struct  LPC_UART1_TypeDef
 Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition. More...
struct  LPC_UART_TypeDef
 Universal Asynchronous Receiver Transmitter (UART) register structure definition. More...
struct  LPC_USB_TypeDef
 Universal Serial Bus (USB) register structure definition. More...
struct  LPC_WDT_TypeDef
 Watchdog Timer (WDT) register structure definition. More...

Macros

#define __MPU_PRESENT   1
#define __NVIC_PRIO_BITS   5
#define __Vendor_SysTickConfig   0
#define IRC_OSC   ( 4000000UL) /* Internal RC oscillator frequency */
#define LPC_ADC   ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define LPC_ADC_BASE   (LPC_APB0_BASE + 0x34000)
#define LPC_AHB_BASE   (0x50000000UL)
#define LPC_AHBRAM0_BASE   (0x2007C000UL)
#define LPC_AHBRAM1_BASE   (0x20080000UL)
#define LPC_APB0_BASE   (0x40000000UL)
#define LPC_APB1_BASE   (0x40080000UL)
#define LPC_CAN1   ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
#define LPC_CAN1_BASE   (LPC_APB0_BASE + 0x44000)
#define LPC_CAN2   ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
#define LPC_CAN2_BASE   (LPC_APB0_BASE + 0x48000)
#define LPC_CANAF   ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
#define LPC_CANAF_BASE   (LPC_APB0_BASE + 0x3C000)
#define LPC_CANAF_RAM   ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
#define LPC_CANAF_RAM_BASE   (LPC_APB0_BASE + 0x38000)
#define LPC_CANCR   ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
#define LPC_CANCR_BASE   (LPC_APB0_BASE + 0x40000)
#define LPC_CM3_BASE   (0xE0000000UL)
#define LPC_DAC   ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
#define LPC_DAC_BASE   (LPC_APB1_BASE + 0x0C000)
#define LPC_EMAC   ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
#define LPC_EMAC_BASE   (LPC_AHB_BASE + 0x00000)
#define LPC_FLASH_BASE   (0x00000000UL)
#define LPC_GPDMA   ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
#define LPC_GPDMA_BASE   (LPC_AHB_BASE + 0x04000)
#define LPC_GPDMACH0   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
#define LPC_GPDMACH0_BASE   (LPC_AHB_BASE + 0x04100)
#define LPC_GPDMACH1   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
#define LPC_GPDMACH1_BASE   (LPC_AHB_BASE + 0x04120)
#define LPC_GPDMACH2   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
#define LPC_GPDMACH2_BASE   (LPC_AHB_BASE + 0x04140)
#define LPC_GPDMACH3   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
#define LPC_GPDMACH3_BASE   (LPC_AHB_BASE + 0x04160)
#define LPC_GPDMACH4   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
#define LPC_GPDMACH4_BASE   (LPC_AHB_BASE + 0x04180)
#define LPC_GPDMACH5   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
#define LPC_GPDMACH5_BASE   (LPC_AHB_BASE + 0x041A0)
#define LPC_GPDMACH6   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
#define LPC_GPDMACH6_BASE   (LPC_AHB_BASE + 0x041C0)
#define LPC_GPDMACH7   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
#define LPC_GPDMACH7_BASE   (LPC_AHB_BASE + 0x041E0)
#define LPC_GPIO0   ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
#define LPC_GPIO0_BASE   (LPC_GPIO_BASE + 0x00000)
#define LPC_GPIO1   ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
#define LPC_GPIO1_BASE   (LPC_GPIO_BASE + 0x00020)
#define LPC_GPIO2   ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
#define LPC_GPIO2_BASE   (LPC_GPIO_BASE + 0x00040)
#define LPC_GPIO3   ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
#define LPC_GPIO3_BASE   (LPC_GPIO_BASE + 0x00060)
#define LPC_GPIO4   ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
#define LPC_GPIO4_BASE   (LPC_GPIO_BASE + 0x00080)
#define LPC_GPIO_BASE   (0x2009C000UL)
#define LPC_GPIOINT   ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
#define LPC_GPIOINT_BASE   (LPC_APB0_BASE + 0x28080)
#define LPC_I2C0   ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
#define LPC_I2C0_BASE   (LPC_APB0_BASE + 0x1C000)
#define LPC_I2C1   ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
#define LPC_I2C1_BASE   (LPC_APB0_BASE + 0x5C000)
#define LPC_I2C2   ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
#define LPC_I2C2_BASE   (LPC_APB1_BASE + 0x20000)
#define LPC_I2S   ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
#define LPC_I2S_BASE   (LPC_APB1_BASE + 0x28000)
#define LPC_MCPWM   ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
#define LPC_MCPWM_BASE   (LPC_APB1_BASE + 0x38000)
#define LPC_PINCON   ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
#define LPC_PINCON_BASE   (LPC_APB0_BASE + 0x2C000)
#define LPC_PWM1   ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
#define LPC_PWM1_BASE   (LPC_APB0_BASE + 0x18000)
#define LPC_QEI   ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
#define LPC_QEI_BASE   (LPC_APB1_BASE + 0x3C000)
#define LPC_RAM_BASE   (0x10000000UL)
#define LPC_RIT   ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
#define LPC_RIT_BASE   (LPC_APB1_BASE + 0x30000)
#define LPC_RTC   ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
#define LPC_RTC_BASE   (LPC_APB0_BASE + 0x24000)
#define LPC_SC   ((LPC_SC_TypeDef *) LPC_SC_BASE )
#define LPC_SC_BASE   (LPC_APB1_BASE + 0x7C000)
#define LPC_SPI   ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
#define LPC_SPI_BASE   (LPC_APB0_BASE + 0x20000)
#define LPC_SSP0   ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
#define LPC_SSP0_BASE   (LPC_APB1_BASE + 0x08000)
#define LPC_SSP1   ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
#define LPC_SSP1_BASE   (LPC_APB0_BASE + 0x30000)
#define LPC_TIM0   ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
#define LPC_TIM0_BASE   (LPC_APB0_BASE + 0x04000)
#define LPC_TIM1   ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
#define LPC_TIM1_BASE   (LPC_APB0_BASE + 0x08000)
#define LPC_TIM2   ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
#define LPC_TIM2_BASE   (LPC_APB1_BASE + 0x10000)
#define LPC_TIM3   ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
#define LPC_TIM3_BASE   (LPC_APB1_BASE + 0x14000)
#define LPC_UART0   ((LPC_UART_TypeDef *) LPC_UART0_BASE )
#define LPC_UART0_BASE   (LPC_APB0_BASE + 0x0C000)
#define LPC_UART1   ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
#define LPC_UART1_BASE   (LPC_APB0_BASE + 0x10000)
#define LPC_UART2   ((LPC_UART_TypeDef *) LPC_UART2_BASE )
#define LPC_UART2_BASE   (LPC_APB1_BASE + 0x18000)
#define LPC_UART3   ((LPC_UART_TypeDef *) LPC_UART3_BASE )
#define LPC_UART3_BASE   (LPC_APB1_BASE + 0x1C000)
#define LPC_USB   ((LPC_USB_TypeDef *) LPC_USB_BASE )
#define LPC_USB_BASE   (LPC_AHB_BASE + 0x0C000)
#define LPC_WDT   ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
#define LPC_WDT_BASE   (LPC_APB0_BASE + 0x00000)
#define OSC_CLK   ( XTAL_HZ) /* Main oscillator frequency */
#define PWMCR_ENABLE_Msk   (1 << 0)
#define PWMCR_RESET_Msk   (1 << 1)
#define PWMIR_MR0I_Msk   (1 << 0)
#define PWMIR_MR1I_Msk   (1 << 1)
#define PWMIR_MR2I_Msk   (1 << 2)
#define PWMIR_MR3I_Msk   (1 << 3)
#define PWMIR_MR4I_Msk   (1 << 8)
#define PWMIR_MR5I_Msk   (1 << 9)
#define PWMIR_MR6I_Msk   (1 << 10)
#define PWMIR_Msk   (0x070F)
#define RTC_CLK   ( 32768UL) /* RTC oscillator frequency */
#define TCCR_CR0_F_Msk   (1 << 1)
#define TCCR_CR0_I_Msk   (1 << 2)
#define TCCR_CR0_R_Msk   (1 << 0)
#define TCCR_CR1_F_Msk   (1 << 4)
#define TCCR_CR1_I_Msk   (1 << 5)
#define TCCR_CR1_R_Msk   (1 << 3)
#define TCCR_CR2_F_Msk   (1 << 7)
#define TCCR_CR2_I_Msk   (1 << 8)
#define TCCR_CR2_R_Msk   (1 << 6)
#define TCCR_CR3_F_Msk   (1 << 10)
#define TCCR_CR3_I_Msk   (1 << 11)
#define TCCR_CR3_R_Msk   (1 << 9)
#define TCR_ENABLE_Msk   (1 << 0)
#define TCR_RESET_Msk   (1 << 1)
#define TIR_CR0I_Msk   (1 << 4)
#define TIR_CR1I_Msk   (1 << 5)
#define TIR_CR2I_Msk   (1 << 6)
#define TIR_CR3I_Msk   (1 << 7)
#define TIR_MR0I_Msk   (1 << 0)
#define TIR_MR1I_Msk   (1 << 1)
#define TIR_MR2I_Msk   (1 << 2)
#define TIR_MR3I_Msk   (1 << 3)
#define TMCR_MR0_I_Msk   (1 << 0)
#define TMCR_MR0_R_Msk   (1 << 1)
#define TMCR_MR0_S_Msk   (1 << 2)
#define TMCR_MR1_I_Msk   (1 << 3)
#define TMCR_MR1_R_Msk   (1 << 4)
#define TMCR_MR1_S_Msk   (1 << 5)
#define TMCR_MR2_I_Msk   (1 << 6)
#define TMCR_MR2_R_Msk   (1 << 7)
#define TMCR_MR2_S_Msk   (1 << 8)
#define TMCR_MR3_I_Msk   (1 << 9)
#define TMCR_MR3_R_Msk   (1 << 10)
#define TMCR_MR3_S_Msk   (1 << 11)
#define WDT_OSC   ( 500000UL) /* Internal WDT oscillator frequency */
#define XTAL_HZ   (12000000UL) /* Oscillator frequency */

Typedefs

typedef enum IRQn IRQn_Type
 IRQ interrupt source definition.

Enumerations

enum  IRQn {
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2,
  SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,
  TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,
  UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,
  CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,
  CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,
  I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2,
  SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,
  TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,
  UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,
  CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,
  CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,
  I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,
  UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,
  SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,
  TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,
  UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,
  CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,
  CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,
  I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,
  UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,
  SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,
  TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,
  UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,
  CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,
  CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,
  I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2,
  SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,
  TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,
  UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,
  CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,
  CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,
  I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,
  UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,
  SysTick_IRQn = -1, WDT_IRQn = 0, RTC_IRQn = 1, TIM0_IRQn = 2,
  TIM2_IRQn = 3, MCIA_IRQn = 4, MCIB_IRQn = 5, UART0_IRQn = 6,
  UART1_IRQn = 7, UART2_IRQn = 8, UART4_IRQn = 9, AACI_IRQn = 10,
  CLCD_IRQn = 11, ENET_IRQn = 12, USBDC_IRQn = 13, USBHC_IRQn = 14,
  CHLCD_IRQn = 15, FLEXRAY_IRQn = 16, CAN_IRQn = 17, LIN_IRQn = 18,
  I2C_IRQn = 19, CPU_CLCD_IRQn = 28, UART3_IRQn = 30, SPI_IRQn = 31,
  NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,
  SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,
  WDT_IRQn = 0, TIMER0_IRQn = 1, TIMER1_IRQn = 2, TIMER2_IRQn = 3,
  TIMER3_IRQn = 4, UART0_IRQn = 5, UART1_IRQn = 6, UART2_IRQn = 7,
  UART3_IRQn = 8, PWM1_IRQn = 9, I2C0_IRQn = 10, I2C1_IRQn = 11,
  I2C2_IRQn = 12, SPI_IRQn = 13, SSP0_IRQn = 14, SSP1_IRQn = 15,
  PLL0_IRQn = 16, RTC_IRQn = 17, EINT0_IRQn = 18, EINT1_IRQn = 19,
  EINT2_IRQn = 20, EINT3_IRQn = 21, ADC_IRQn = 22, BOD_IRQn = 23,
  USB_IRQn = 24, CAN_IRQn = 25, DMA_IRQn = 26, I2S_IRQn = 27,
  ENET_IRQn = 28, RIT_IRQn = 29, MCPWM_IRQn = 30, QEI_IRQn = 31,
  PLL1_IRQn = 32, USBActivity_IRQn = 33, CANActivity_IRQn = 34, WDT_IRQn = 0,
  PROGRAMM_INT_IRQn = 1, ARM_CORE_ICE_RX_IRQn = 2, ARM_CORE_ICE_TX_IRQn = 3, TIMER0_IRQn = 4,
  TIMER1_IRQn = 5, UART0_IRQn = 6, UART1_IRQn = 7, PWM_IRQn = 8,
  PWM0_IRQn = 8, I2C_IRQn = 9, I2C0_IRQn = 9, SPI_IRQn = 10,
  SPI0_IRQn = 10, SSP0_IRQn = 10, SPI1_IRQn = 11, SSP1_IRQn = 11,
  PLL0_IRQn = 12, RTC_IRQn = 13, EINT0_IRQn = 14, EINT1_IRQn = 15,
  EINT2_IRQn = 16, EINT3_IRQn = 17, ADC_IRQn = 18, CAN1_TX = 20,
  CAN2_TX_IRQn = 21, CAN3_TX_IRQn = 22, CAN4_TX_IRQn = 23, RESERVE_23_IRQn = 24,
  RESERVE_24_IRQn = 25, CAN1_RX_IRQn = 26, CAN2_RX_IRQn = 27, CAN3_RX_IRQn = 28,
  CAN4_RX_IRQn = 29
}
 IRQ interrupt source definition. More...

Functions

void SystemCoreClockUpdate (void)
 Update SystemCoreClock variable.
void SystemInit (void)
 Initialize the system.

Variables

uint32_t SystemCoreClock

Detailed Description

Macro Definition Documentation

#define __MPU_PRESENT   1

MPU present or not

Definition at line 105 of file LPC17xx.h.

#define __NVIC_PRIO_BITS   5

Number of Bits used for Priority Levels

Definition at line 106 of file LPC17xx.h.

#define __Vendor_SysTickConfig   0

Set to 1 if different SysTick Config is used

Definition at line 107 of file LPC17xx.h.

#define IRC_OSC   ( 4000000UL) /* Internal RC oscillator frequency */

Definition at line 85 of file system_LPC17xx.h.

#define LPC_ADC   ((LPC_ADC_TypeDef *) LPC_ADC_BASE )

Definition at line 1115 of file LPC17xx.h.

#define LPC_ADC_BASE   (LPC_APB0_BASE + 0x34000)

Definition at line 1043 of file LPC17xx.h.

#define LPC_AHB_BASE   (0x50000000UL)

Definition at line 1027 of file LPC17xx.h.

#define LPC_AHBRAM0_BASE   (0x2007C000UL)

Definition at line 1021 of file LPC17xx.h.

#define LPC_AHBRAM1_BASE   (0x20080000UL)

Definition at line 1022 of file LPC17xx.h.

#define LPC_APB0_BASE   (0x40000000UL)

Definition at line 1025 of file LPC17xx.h.

#define LPC_APB1_BASE   (0x40080000UL)

Definition at line 1026 of file LPC17xx.h.

#define LPC_CAN1   ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )

Definition at line 1120 of file LPC17xx.h.

#define LPC_CAN1_BASE   (LPC_APB0_BASE + 0x44000)

Definition at line 1047 of file LPC17xx.h.

#define LPC_CAN2   ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )

Definition at line 1121 of file LPC17xx.h.

#define LPC_CAN2_BASE   (LPC_APB0_BASE + 0x48000)

Definition at line 1048 of file LPC17xx.h.

#define LPC_CANAF   ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )

Definition at line 1118 of file LPC17xx.h.

#define LPC_CANAF_BASE   (LPC_APB0_BASE + 0x3C000)

Definition at line 1045 of file LPC17xx.h.

#define LPC_CANAF_RAM   ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)

Definition at line 1117 of file LPC17xx.h.

#define LPC_CANAF_RAM_BASE   (LPC_APB0_BASE + 0x38000)

Definition at line 1044 of file LPC17xx.h.

#define LPC_CANCR   ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )

Definition at line 1119 of file LPC17xx.h.

#define LPC_CANCR_BASE   (LPC_APB0_BASE + 0x40000)

Definition at line 1046 of file LPC17xx.h.

#define LPC_CM3_BASE   (0xE0000000UL)

Definition at line 1028 of file LPC17xx.h.

#define LPC_DAC   ((LPC_DAC_TypeDef *) LPC_DAC_BASE )

Definition at line 1116 of file LPC17xx.h.

#define LPC_DAC_BASE   (LPC_APB1_BASE + 0x0C000)

Definition at line 1053 of file LPC17xx.h.

#define LPC_EMAC   ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )

Definition at line 1124 of file LPC17xx.h.

#define LPC_EMAC_BASE   (LPC_AHB_BASE + 0x00000)

Definition at line 1066 of file LPC17xx.h.

#define LPC_FLASH_BASE   (0x00000000UL)

Definition at line 1015 of file LPC17xx.h.

#define LPC_GPDMA   ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )

Definition at line 1125 of file LPC17xx.h.

#define LPC_GPDMA_BASE   (LPC_AHB_BASE + 0x04000)

Definition at line 1067 of file LPC17xx.h.

#define LPC_GPDMACH0   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )

Definition at line 1126 of file LPC17xx.h.

#define LPC_GPDMACH0_BASE   (LPC_AHB_BASE + 0x04100)

Definition at line 1068 of file LPC17xx.h.

#define LPC_GPDMACH1   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )

Definition at line 1127 of file LPC17xx.h.

#define LPC_GPDMACH1_BASE   (LPC_AHB_BASE + 0x04120)

Definition at line 1069 of file LPC17xx.h.

#define LPC_GPDMACH2   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )

Definition at line 1128 of file LPC17xx.h.

#define LPC_GPDMACH2_BASE   (LPC_AHB_BASE + 0x04140)

Definition at line 1070 of file LPC17xx.h.

#define LPC_GPDMACH3   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )

Definition at line 1129 of file LPC17xx.h.

#define LPC_GPDMACH3_BASE   (LPC_AHB_BASE + 0x04160)

Definition at line 1071 of file LPC17xx.h.

#define LPC_GPDMACH4   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )

Definition at line 1130 of file LPC17xx.h.

#define LPC_GPDMACH4_BASE   (LPC_AHB_BASE + 0x04180)

Definition at line 1072 of file LPC17xx.h.

#define LPC_GPDMACH5   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )

Definition at line 1131 of file LPC17xx.h.

#define LPC_GPDMACH5_BASE   (LPC_AHB_BASE + 0x041A0)

Definition at line 1073 of file LPC17xx.h.

#define LPC_GPDMACH6   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )

Definition at line 1132 of file LPC17xx.h.

#define LPC_GPDMACH6_BASE   (LPC_AHB_BASE + 0x041C0)

Definition at line 1074 of file LPC17xx.h.

#define LPC_GPDMACH7   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )

Definition at line 1133 of file LPC17xx.h.

#define LPC_GPDMACH7_BASE   (LPC_AHB_BASE + 0x041E0)

Definition at line 1075 of file LPC17xx.h.

#define LPC_GPIO0   ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )

Definition at line 1089 of file LPC17xx.h.

#define LPC_GPIO0_BASE   (LPC_GPIO_BASE + 0x00000)

Definition at line 1079 of file LPC17xx.h.

#define LPC_GPIO1   ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )

Definition at line 1090 of file LPC17xx.h.

#define LPC_GPIO1_BASE   (LPC_GPIO_BASE + 0x00020)

Definition at line 1080 of file LPC17xx.h.

#define LPC_GPIO2   ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )

Definition at line 1091 of file LPC17xx.h.

#define LPC_GPIO2_BASE   (LPC_GPIO_BASE + 0x00040)

Definition at line 1081 of file LPC17xx.h.

#define LPC_GPIO3   ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )

Definition at line 1092 of file LPC17xx.h.

#define LPC_GPIO3_BASE   (LPC_GPIO_BASE + 0x00060)

Definition at line 1082 of file LPC17xx.h.

#define LPC_GPIO4   ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )

Definition at line 1093 of file LPC17xx.h.

#define LPC_GPIO4_BASE   (LPC_GPIO_BASE + 0x00080)

Definition at line 1083 of file LPC17xx.h.

#define LPC_GPIO_BASE   (0x2009C000UL)

Definition at line 1024 of file LPC17xx.h.

#define LPC_GPIOINT   ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )

Definition at line 1111 of file LPC17xx.h.

#define LPC_GPIOINT_BASE   (LPC_APB0_BASE + 0x28080)

Definition at line 1040 of file LPC17xx.h.

#define LPC_I2C0   ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )

Definition at line 1105 of file LPC17xx.h.

#define LPC_I2C0_BASE   (LPC_APB0_BASE + 0x1C000)

Definition at line 1037 of file LPC17xx.h.

#define LPC_I2C1   ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )

Definition at line 1106 of file LPC17xx.h.

#define LPC_I2C1_BASE   (LPC_APB0_BASE + 0x5C000)

Definition at line 1049 of file LPC17xx.h.

#define LPC_I2C2   ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )

Definition at line 1107 of file LPC17xx.h.

#define LPC_I2C2_BASE   (LPC_APB1_BASE + 0x20000)

Definition at line 1058 of file LPC17xx.h.

#define LPC_I2S   ((LPC_I2S_TypeDef *) LPC_I2S_BASE )

Definition at line 1108 of file LPC17xx.h.

#define LPC_I2S_BASE   (LPC_APB1_BASE + 0x28000)

Definition at line 1059 of file LPC17xx.h.

#define LPC_MCPWM   ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )

Definition at line 1122 of file LPC17xx.h.

#define LPC_MCPWM_BASE   (LPC_APB1_BASE + 0x38000)

Definition at line 1061 of file LPC17xx.h.

#define LPC_PINCON   ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )

Definition at line 1112 of file LPC17xx.h.

#define LPC_PINCON_BASE   (LPC_APB0_BASE + 0x2C000)

Definition at line 1041 of file LPC17xx.h.

#define LPC_PWM1   ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )

Definition at line 1104 of file LPC17xx.h.

#define LPC_PWM1_BASE   (LPC_APB0_BASE + 0x18000)

Definition at line 1036 of file LPC17xx.h.

#define LPC_QEI   ((LPC_QEI_TypeDef *) LPC_QEI_BASE )

Definition at line 1123 of file LPC17xx.h.

#define LPC_QEI_BASE   (LPC_APB1_BASE + 0x3C000)

Definition at line 1062 of file LPC17xx.h.

#define LPC_RAM_BASE   (0x10000000UL)

Definition at line 1016 of file LPC17xx.h.

#define LPC_RIT   ((LPC_RIT_TypeDef *) LPC_RIT_BASE )

Definition at line 1099 of file LPC17xx.h.

#define LPC_RIT_BASE   (LPC_APB1_BASE + 0x30000)

Definition at line 1060 of file LPC17xx.h.

#define LPC_RTC   ((LPC_RTC_TypeDef *) LPC_RTC_BASE )

Definition at line 1110 of file LPC17xx.h.

#define LPC_RTC_BASE   (LPC_APB0_BASE + 0x24000)

Definition at line 1039 of file LPC17xx.h.

#define LPC_SC   ((LPC_SC_TypeDef *) LPC_SC_BASE )

Definition at line 1088 of file LPC17xx.h.

Referenced by SystemCoreClockUpdate(), and SystemInit().

#define LPC_SC_BASE   (LPC_APB1_BASE + 0x7C000)

Definition at line 1063 of file LPC17xx.h.

#define LPC_SPI   ((LPC_SPI_TypeDef *) LPC_SPI_BASE )

Definition at line 1109 of file LPC17xx.h.

#define LPC_SPI_BASE   (LPC_APB0_BASE + 0x20000)

Definition at line 1038 of file LPC17xx.h.

#define LPC_SSP0   ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )

Definition at line 1113 of file LPC17xx.h.

#define LPC_SSP0_BASE   (LPC_APB1_BASE + 0x08000)

Definition at line 1052 of file LPC17xx.h.

#define LPC_SSP1   ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )

Definition at line 1114 of file LPC17xx.h.

#define LPC_SSP1_BASE   (LPC_APB0_BASE + 0x30000)

Definition at line 1042 of file LPC17xx.h.

#define LPC_TIM0   ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )

Definition at line 1095 of file LPC17xx.h.

#define LPC_TIM0_BASE   (LPC_APB0_BASE + 0x04000)

Definition at line 1032 of file LPC17xx.h.

#define LPC_TIM1   ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )

Definition at line 1096 of file LPC17xx.h.

#define LPC_TIM1_BASE   (LPC_APB0_BASE + 0x08000)

Definition at line 1033 of file LPC17xx.h.

#define LPC_TIM2   ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )

Definition at line 1097 of file LPC17xx.h.

#define LPC_TIM2_BASE   (LPC_APB1_BASE + 0x10000)

Definition at line 1054 of file LPC17xx.h.

#define LPC_TIM3   ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )

Definition at line 1098 of file LPC17xx.h.

#define LPC_TIM3_BASE   (LPC_APB1_BASE + 0x14000)

Definition at line 1055 of file LPC17xx.h.

#define LPC_UART0   ((LPC_UART_TypeDef *) LPC_UART0_BASE )

Definition at line 1100 of file LPC17xx.h.

#define LPC_UART0_BASE   (LPC_APB0_BASE + 0x0C000)

Definition at line 1034 of file LPC17xx.h.

#define LPC_UART1   ((LPC_UART1_TypeDef *) LPC_UART1_BASE )

Definition at line 1101 of file LPC17xx.h.

#define LPC_UART1_BASE   (LPC_APB0_BASE + 0x10000)

Definition at line 1035 of file LPC17xx.h.

#define LPC_UART2   ((LPC_UART_TypeDef *) LPC_UART2_BASE )

Definition at line 1102 of file LPC17xx.h.

#define LPC_UART2_BASE   (LPC_APB1_BASE + 0x18000)

Definition at line 1056 of file LPC17xx.h.

#define LPC_UART3   ((LPC_UART_TypeDef *) LPC_UART3_BASE )

Definition at line 1103 of file LPC17xx.h.

#define LPC_UART3_BASE   (LPC_APB1_BASE + 0x1C000)

Definition at line 1057 of file LPC17xx.h.

#define LPC_USB   ((LPC_USB_TypeDef *) LPC_USB_BASE )

Definition at line 1134 of file LPC17xx.h.

#define LPC_USB_BASE   (LPC_AHB_BASE + 0x0C000)

Definition at line 1076 of file LPC17xx.h.

#define LPC_WDT   ((LPC_WDT_TypeDef *) LPC_WDT_BASE )

Definition at line 1094 of file LPC17xx.h.

#define LPC_WDT_BASE   (LPC_APB0_BASE + 0x00000)

Definition at line 1031 of file LPC17xx.h.

#define OSC_CLK   ( XTAL_HZ) /* Main oscillator frequency */

Definition at line 79 of file system_LPC17xx.h.

#define PWMCR_ENABLE_Msk   (1 << 0)

Definition at line 364 of file LPC17xx.h.

#define PWMCR_RESET_Msk   (1 << 1)

Definition at line 365 of file LPC17xx.h.

#define PWMIR_MR0I_Msk   (1 << 0)

Definition at line 299 of file LPC17xx.h.

#define PWMIR_MR1I_Msk   (1 << 1)

Definition at line 300 of file LPC17xx.h.

#define PWMIR_MR2I_Msk   (1 << 2)

Definition at line 301 of file LPC17xx.h.

#define PWMIR_MR3I_Msk   (1 << 3)

Definition at line 302 of file LPC17xx.h.

#define PWMIR_MR4I_Msk   (1 << 8)

Definition at line 303 of file LPC17xx.h.

#define PWMIR_MR5I_Msk   (1 << 9)

Definition at line 304 of file LPC17xx.h.

#define PWMIR_MR6I_Msk   (1 << 10)

Definition at line 305 of file LPC17xx.h.

#define PWMIR_Msk   (0x070F)

Definition at line 306 of file LPC17xx.h.

#define RTC_CLK   ( 32768UL) /* RTC oscillator frequency */

Definition at line 82 of file system_LPC17xx.h.

#define TCCR_CR0_F_Msk   (1 << 1)

Definition at line 328 of file LPC17xx.h.

#define TCCR_CR0_I_Msk   (1 << 2)

Definition at line 329 of file LPC17xx.h.

#define TCCR_CR0_R_Msk   (1 << 0)

Definition at line 327 of file LPC17xx.h.

#define TCCR_CR1_F_Msk   (1 << 4)

Definition at line 331 of file LPC17xx.h.

#define TCCR_CR1_I_Msk   (1 << 5)

Definition at line 332 of file LPC17xx.h.

#define TCCR_CR1_R_Msk   (1 << 3)

Definition at line 330 of file LPC17xx.h.

#define TCCR_CR2_F_Msk   (1 << 7)

Definition at line 334 of file LPC17xx.h.

#define TCCR_CR2_I_Msk   (1 << 8)

Definition at line 335 of file LPC17xx.h.

#define TCCR_CR2_R_Msk   (1 << 6)

Definition at line 333 of file LPC17xx.h.

#define TCCR_CR3_F_Msk   (1 << 10)

Definition at line 337 of file LPC17xx.h.

#define TCCR_CR3_I_Msk   (1 << 11)

Definition at line 338 of file LPC17xx.h.

#define TCCR_CR3_R_Msk   (1 << 9)

Definition at line 336 of file LPC17xx.h.

#define TCR_ENABLE_Msk   (1 << 0)

Definition at line 309 of file LPC17xx.h.

#define TCR_RESET_Msk   (1 << 1)

Definition at line 310 of file LPC17xx.h.

#define TIR_CR0I_Msk   (1 << 4)

Definition at line 293 of file LPC17xx.h.

#define TIR_CR1I_Msk   (1 << 5)

Definition at line 294 of file LPC17xx.h.

#define TIR_CR2I_Msk   (1 << 6)

Definition at line 295 of file LPC17xx.h.

#define TIR_CR3I_Msk   (1 << 7)

Definition at line 296 of file LPC17xx.h.

#define TIR_MR0I_Msk   (1 << 0)

Definition at line 289 of file LPC17xx.h.

#define TIR_MR1I_Msk   (1 << 1)

Definition at line 290 of file LPC17xx.h.

#define TIR_MR2I_Msk   (1 << 2)

Definition at line 291 of file LPC17xx.h.

#define TIR_MR3I_Msk   (1 << 3)

Definition at line 292 of file LPC17xx.h.

#define TMCR_MR0_I_Msk   (1 << 0)

Definition at line 313 of file LPC17xx.h.

#define TMCR_MR0_R_Msk   (1 << 1)

Definition at line 314 of file LPC17xx.h.

#define TMCR_MR0_S_Msk   (1 << 2)

Definition at line 315 of file LPC17xx.h.

#define TMCR_MR1_I_Msk   (1 << 3)

Definition at line 316 of file LPC17xx.h.

#define TMCR_MR1_R_Msk   (1 << 4)

Definition at line 317 of file LPC17xx.h.

#define TMCR_MR1_S_Msk   (1 << 5)

Definition at line 318 of file LPC17xx.h.

#define TMCR_MR2_I_Msk   (1 << 6)

Definition at line 319 of file LPC17xx.h.

#define TMCR_MR2_R_Msk   (1 << 7)

Definition at line 320 of file LPC17xx.h.

#define TMCR_MR2_S_Msk   (1 << 8)

Definition at line 321 of file LPC17xx.h.

#define TMCR_MR3_I_Msk   (1 << 9)

Definition at line 322 of file LPC17xx.h.

#define TMCR_MR3_R_Msk   (1 << 10)

Definition at line 323 of file LPC17xx.h.

#define TMCR_MR3_S_Msk   (1 << 11)

Definition at line 324 of file LPC17xx.h.

#define WDT_OSC   ( 500000UL) /* Internal WDT oscillator frequency */

Definition at line 88 of file system_LPC17xx.h.

#define XTAL_HZ   (12000000UL) /* Oscillator frequency */

Definition at line 76 of file system_LPC17xx.h.

Typedef Documentation

typedef enum IRQn IRQn_Type

IRQ interrupt source definition.

Enumeration Type Documentation

enum IRQn

IRQ interrupt source definition.

Enumerator:
NonMaskableInt_IRQn 

2 Non Maskable Interrupt

HardFault_IRQn 

3 HardFault Interrupt

SVCall_IRQn 

11 SV Call Interrupt

PendSV_IRQn 

14 Pend SV Interrupt

SysTick_IRQn 

15 System Tick Interrupt

WDT_IRQn 

Watchdog Timer Interrupt

RTC_IRQn 

Real Time Clock Interrupt

TIM0_IRQn 

Timer0 / Timer1 Interrupt

TIM2_IRQn 

Timer2 / Timer3 Interrupt

MCIA_IRQn 

MCIa Interrupt

MCIB_IRQn 

MCIb Interrupt

UART0_IRQn 

UART0 Interrupt

UART1_IRQn 

UART1 Interrupt

UART2_IRQn 

UART2 Interrupt

UART4_IRQn 

UART4 Interrupt

AACI_IRQn 

AACI / AC97 Interrupt

CLCD_IRQn 

CLCD Combined Interrupt

ENET_IRQn 

Ethernet Interrupt

USBDC_IRQn 

USB Device Interrupt

USBHC_IRQn 

USB Host Controller Interrupt

CHLCD_IRQn 

Character LCD Interrupt

FLEXRAY_IRQn 

Flexray Interrupt

CAN_IRQn 

CAN Interrupt

LIN_IRQn 

LIN Interrupt

I2C_IRQn 

I2C ADC/DAC Interrupt

CPU_CLCD_IRQn 

CPU CLCD Combined Interrupt

UART3_IRQn 

UART3 Interrupt

SPI_IRQn 

SPI Touchscreen Interrupt

NonMaskableInt_IRQn 

2 Non Maskable Interrupt

HardFault_IRQn 

3 HardFault Interrupt

SVCall_IRQn 

11 SV Call Interrupt

PendSV_IRQn 

14 Pend SV Interrupt

SysTick_IRQn 

15 System Tick Interrupt

WDT_IRQn 

Watchdog Timer Interrupt

RTC_IRQn 

Real Time Clock Interrupt

TIM0_IRQn 

Timer0 / Timer1 Interrupt

TIM2_IRQn 

Timer2 / Timer3 Interrupt

MCIA_IRQn 

MCIa Interrupt

MCIB_IRQn 

MCIb Interrupt

UART0_IRQn 

UART0 Interrupt

UART1_IRQn 

UART1 Interrupt

UART2_IRQn 

UART2 Interrupt

UART4_IRQn 

UART4 Interrupt

AACI_IRQn 

AACI / AC97 Interrupt

CLCD_IRQn 

CLCD Combined Interrupt

ENET_IRQn 

Ethernet Interrupt

USBDC_IRQn 

USB Device Interrupt

USBHC_IRQn 

USB Host Controller Interrupt

CHLCD_IRQn 

Character LCD Interrupt

FLEXRAY_IRQn 

Flexray Interrupt

CAN_IRQn 

CAN Interrupt

LIN_IRQn 

LIN Interrupt

I2C_IRQn 

I2C ADC/DAC Interrupt

CPU_CLCD_IRQn 

CPU CLCD Combined Interrupt

UART3_IRQn 

UART3 Interrupt

SPI_IRQn 

SPI Touchscreen Interrupt

NonMaskableInt_IRQn 

2 Non Maskable Interrupt

HardFault_IRQn 

3 HardFault Interrupt

MemoryManagement_IRQn 

4 Memory Management Interrupt

BusFault_IRQn 

5 Bus Fault Interrupt

UsageFault_IRQn 

6 Usage Fault Interrupt

SVCall_IRQn 

11 SV Call Interrupt

DebugMonitor_IRQn 

12 Debug Monitor Interrupt

PendSV_IRQn 

14 Pend SV Interrupt

SysTick_IRQn 

15 System Tick Interrupt

WDT_IRQn 

Watchdog Timer Interrupt

RTC_IRQn 

Real Time Clock Interrupt

TIM0_IRQn 

Timer0 / Timer1 Interrupt

TIM2_IRQn 

Timer2 / Timer3 Interrupt

MCIA_IRQn 

MCIa Interrupt

MCIB_IRQn 

MCIb Interrupt

UART0_IRQn 

UART0 Interrupt

UART1_IRQn 

UART1 Interrupt

UART2_IRQn 

UART2 Interrupt

UART4_IRQn 

UART4 Interrupt

AACI_IRQn 

AACI / AC97 Interrupt

CLCD_IRQn 

CLCD Combined Interrupt

ENET_IRQn 

Ethernet Interrupt

USBDC_IRQn 

USB Device Interrupt

USBHC_IRQn 

USB Host Controller Interrupt

CHLCD_IRQn 

Character LCD Interrupt

FLEXRAY_IRQn 

Flexray Interrupt

CAN_IRQn 

CAN Interrupt

LIN_IRQn 

LIN Interrupt

I2C_IRQn 

I2C ADC/DAC Interrupt

CPU_CLCD_IRQn 

CPU CLCD Combined Interrupt

UART3_IRQn 

UART3 Interrupt

SPI_IRQn 

SPI Touchscreen Interrupt

NonMaskableInt_IRQn 

2 Non Maskable Interrupt

HardFault_IRQn 

3 HardFault Interrupt

MemoryManagement_IRQn 

4 Memory Management Interrupt

BusFault_IRQn 

5 Bus Fault Interrupt

UsageFault_IRQn 

6 Usage Fault Interrupt

SVCall_IRQn 

11 SV Call Interrupt

DebugMonitor_IRQn 

12 Debug Monitor Interrupt

PendSV_IRQn 

14 Pend SV Interrupt

SysTick_IRQn 

15 System Tick Interrupt

WDT_IRQn 

Watchdog Timer Interrupt

RTC_IRQn 

Real Time Clock Interrupt

TIM0_IRQn 

Timer0 / Timer1 Interrupt

TIM2_IRQn 

Timer2 / Timer3 Interrupt

MCIA_IRQn 

MCIa Interrupt

MCIB_IRQn 

MCIb Interrupt

UART0_IRQn 

UART0 Interrupt

UART1_IRQn 

UART1 Interrupt

UART2_IRQn 

UART2 Interrupt

UART4_IRQn 

UART4 Interrupt

AACI_IRQn 

AACI / AC97 Interrupt

CLCD_IRQn 

CLCD Combined Interrupt

ENET_IRQn 

Ethernet Interrupt

USBDC_IRQn 

USB Device Interrupt

USBHC_IRQn 

USB Host Controller Interrupt

CHLCD_IRQn 

Character LCD Interrupt

FLEXRAY_IRQn 

Flexray Interrupt

CAN_IRQn 

CAN Interrupt

LIN_IRQn 

LIN Interrupt

I2C_IRQn 

I2C ADC/DAC Interrupt

CPU_CLCD_IRQn 

CPU CLCD Combined Interrupt

UART3_IRQn 

UART3 Interrupt

SPI_IRQn 

SPI Touchscreen Interrupt

NonMaskableInt_IRQn 

2 Non Maskable Interrupt

HardFault_IRQn 

3 HardFault Interrupt

SVCall_IRQn 

11 SV Call Interrupt

PendSV_IRQn 

14 Pend SV Interrupt

SysTick_IRQn 

15 System Tick Interrupt

WDT_IRQn 

Watchdog Timer Interrupt

RTC_IRQn 

Real Time Clock Interrupt

TIM0_IRQn 

Timer0 / Timer1 Interrupt

TIM2_IRQn 

Timer2 / Timer3 Interrupt

MCIA_IRQn 

MCIa Interrupt

MCIB_IRQn 

MCIb Interrupt

UART0_IRQn 

UART0 Interrupt

UART1_IRQn 

UART1 Interrupt

UART2_IRQn 

UART2 Interrupt

UART4_IRQn 

UART4 Interrupt

AACI_IRQn 

AACI / AC97 Interrupt

CLCD_IRQn 

CLCD Combined Interrupt

ENET_IRQn 

Ethernet Interrupt

USBDC_IRQn 

USB Device Interrupt

USBHC_IRQn 

USB Host Controller Interrupt

CHLCD_IRQn 

Character LCD Interrupt

FLEXRAY_IRQn 

Flexray Interrupt

CAN_IRQn 

CAN Interrupt

LIN_IRQn 

LIN Interrupt

I2C_IRQn 

I2C ADC/DAC Interrupt

CPU_CLCD_IRQn 

CPU CLCD Combined Interrupt

UART3_IRQn 

UART3 Interrupt

SPI_IRQn 

SPI Touchscreen Interrupt

NonMaskableInt_IRQn 

2 Non Maskable Interrupt

HardFault_IRQn 

3 HardFault Interrupt

MemoryManagement_IRQn 

4 Memory Management Interrupt

BusFault_IRQn 

5 Bus Fault Interrupt

UsageFault_IRQn 

6 Usage Fault Interrupt

SVCall_IRQn 

11 SV Call Interrupt

DebugMonitor_IRQn 

12 Debug Monitor Interrupt

PendSV_IRQn 

14 Pend SV Interrupt

SysTick_IRQn 

15 System Tick Interrupt

WDT_IRQn 

Watchdog Timer Interrupt

RTC_IRQn 

Real Time Clock Interrupt

TIM0_IRQn 

Timer0 / Timer1 Interrupt

TIM2_IRQn 

Timer2 / Timer3 Interrupt

MCIA_IRQn 

MCIa Interrupt

MCIB_IRQn 

MCIb Interrupt

UART0_IRQn 

UART0 Interrupt

UART1_IRQn 

UART1 Interrupt

UART2_IRQn 

UART2 Interrupt

UART4_IRQn 

UART4 Interrupt

AACI_IRQn 

AACI / AC97 Interrupt

CLCD_IRQn 

CLCD Combined Interrupt

ENET_IRQn 

Ethernet Interrupt

USBDC_IRQn 

USB Device Interrupt

USBHC_IRQn 

USB Host Controller Interrupt

CHLCD_IRQn 

Character LCD Interrupt

FLEXRAY_IRQn 

Flexray Interrupt

CAN_IRQn 

CAN Interrupt

LIN_IRQn 

LIN Interrupt

I2C_IRQn 

I2C ADC/DAC Interrupt

CPU_CLCD_IRQn 

CPU CLCD Combined Interrupt

UART3_IRQn 

UART3 Interrupt

SPI_IRQn 

SPI Touchscreen Interrupt

NonMaskableInt_IRQn 

2 Non Maskable Interrupt

MemoryManagement_IRQn 

4 Cortex-M3 Memory Management Interrupt

BusFault_IRQn 

5 Cortex-M3 Bus Fault Interrupt

UsageFault_IRQn 

6 Cortex-M3 Usage Fault Interrupt

SVCall_IRQn 

11 Cortex-M3 SV Call Interrupt

DebugMonitor_IRQn 

12 Cortex-M3 Debug Monitor Interrupt

PendSV_IRQn 

14 Cortex-M3 Pend SV Interrupt

SysTick_IRQn 

15 Cortex-M3 System Tick Interrupt

WDT_IRQn 

Watchdog Timer Interrupt

TIMER0_IRQn 

Timer0 Interrupt

TIMER1_IRQn 

Timer1 Interrupt

TIMER2_IRQn 

Timer2 Interrupt

TIMER3_IRQn 

Timer3 Interrupt

UART0_IRQn 

UART0 Interrupt

UART1_IRQn 

UART1 Interrupt

UART2_IRQn 

UART2 Interrupt

UART3_IRQn 

UART3 Interrupt

PWM1_IRQn 

PWM1 Interrupt

I2C0_IRQn 

I2C0 Interrupt

I2C1_IRQn 

I2C1 Interrupt

I2C2_IRQn 

I2C2 Interrupt

SPI_IRQn 

SPI Interrupt

SSP0_IRQn 

SSP0 Interrupt

SSP1_IRQn 

SSP1 Interrupt

PLL0_IRQn 

PLL0 Lock (Main PLL) Interrupt

RTC_IRQn 

Real Time Clock Interrupt

EINT0_IRQn 

External Interrupt 0 Interrupt

EINT1_IRQn 

External Interrupt 1 Interrupt

EINT2_IRQn 

External Interrupt 2 Interrupt

EINT3_IRQn 

External Interrupt 3 Interrupt

ADC_IRQn 

A/D Converter Interrupt

BOD_IRQn 

Brown-Out Detect Interrupt

USB_IRQn 

USB Interrupt

CAN_IRQn 

CAN Interrupt

DMA_IRQn 

General Purpose DMA Interrupt

I2S_IRQn 

I2S Interrupt

ENET_IRQn 

Ethernet Interrupt

RIT_IRQn 

Repetitive Interrupt Timer Interrupt

MCPWM_IRQn 

Motor Control PWM Interrupt

QEI_IRQn 

Quadrature Encoder Interface Interrupt

PLL1_IRQn 

PLL1 Lock (USB PLL) Interrupt

USBActivity_IRQn 

USB Activity Interrupt

CANActivity_IRQn 

CAN Activity Interrupt

WDT_IRQn 

Watchdog Timer Interrupt

PROGRAMM_INT_IRQn 
ARM_CORE_ICE_RX_IRQn 
ARM_CORE_ICE_TX_IRQn 
TIMER0_IRQn 

Timer0 Interrupt

TIMER1_IRQn 

Timer1 Interrupt

UART0_IRQn 

UART0 Interrupt

UART1_IRQn 

UART1 Interrupt

PWM_IRQn 

PWM Interrupt

PWM0_IRQn 

PWM0 Interrupt

I2C_IRQn 

I2C Interrupt

I2C0_IRQn 

I2C0 Interrupt

SPI_IRQn 

SPI Interrupt

SPI0_IRQn 

SPI0 Interrupt

SSP0_IRQn 

SSP0 Interrupt

SPI1_IRQn 

SPI1 Interrupt

SSP1_IRQn 

SSP1 Interrupt

PLL0_IRQn 

PLL0 Lock (Main PLL) Interrupt

RTC_IRQn 

Real Time Clock Interrupt

EINT0_IRQn 

External Interrupt 0 Interrupt

EINT1_IRQn 

External Interrupt 1 Interrupt

EINT2_IRQn 

External Interrupt 2 Interrupt

EINT3_IRQn 

External Interrupt 3 Interrupt

ADC_IRQn 

A/D Converter Interrupt

CAN1_TX 
CAN2_TX_IRQn 
CAN3_TX_IRQn 
CAN4_TX_IRQn 
RESERVE_23_IRQn 
RESERVE_24_IRQn 
CAN1_RX_IRQn 
CAN2_RX_IRQn 
CAN3_RX_IRQn 
CAN4_RX_IRQn 

Definition at line 47 of file LPC17xx.h.

Function Documentation

void SystemCoreClockUpdate ( void  )

Update SystemCoreClock variable.

Parameters
none
Returns
none

Updates the SystemCoreClock with current core Clock retrieved from cpu registers.

Definition at line 45 of file system_ARMCM0.c.

References __SYSTEM_CLOCK, IRC_OSC, LPC_SC, OSC_CLK, RTC_CLK, and SystemCoreClock.

void SystemInit ( void  )

Initialize the system.

Parameters
none
Returns
none

Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable.

Parameters
none
Returns
none

Setup the microcontroller system. Initialize the System.

Returns
none

Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable.

Definition at line 61 of file system_ARMCM0.c.

Variable Documentation

uint32_t SystemCoreClock

System Clock Frequency (Core Clock)

Definition at line 39 of file system_ARMCM0.c.