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lpc2xxx_old.h
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1 /*
2  * CMSIS2000
3  * CMSIS-like sources for LPC2xxx series MCUs
4  *
5  * (C) Copyright 2011-2012, Dmitriy Cherepanov, All Rights Reserved
6  *
7  * Version: 0.0.7
8  * Date of the Last Update: 2013-03-04
9  *
10  * Permission is hereby granted, free of charge, to any person obtaining a copy
11  * of this software and associated documentation files (the "Software"), to
12  * deal in the Software without restriction, including without limitation the
13  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
14  * sell copies of the Software, and to permit persons to whom the Software is
15  * furnished to do so, subject to the following conditions:
16  *
17  * The above copyright notice and this permission notice shall be included in
18  * all copies or substantial portions of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
23  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26  * IN THE SOFTWARE.
27  *
28  * Do not be lasy! For the latest version see http://irtos.sourceforge.net .
29  *
30  *
31 #*/
32 
33 #ifndef _ARCH_ARM_NXP_LPC2XXX_H_
34 #define _ARCH_ARM_NXP_LPC2XXX_H_ 1
35 /*-----------Документация Doxygen -- Doxygen documentation -----------------*/
36 /** \file
37  *\~russian
38  * Адреса перефирийных регистров в LPC
39  *\~english
40  * APB(ARM Peripheral Bus) peripheries registers addresses
41  *\~
42  * \author Dmitriy Cherepanov
43  * \date 2010
44  * \ingroup xgportARM7_NXP
45  *\~russian
46  * \addtogroup xgportARM7_NXP Старый исходный код от NXP
47  *\~english
48  * \addtogroup xgportARM7_NXP OLD Sources from NXP
49  *\~
50 
51  * @{
52  */
53 /** \ingroup xgportARM7_NXP
54  *\if russian_lng
55  * \defgroup reg_addresses_LPC2000_old Адреса перефирийных регистров в LPC
56  *\else
57  * \defgroup reg_addresses_LPC2000_old APB(ARM Peripheral Bus) peripheries registers addresses
58  *\endif
59  * \addtogroup reg_addresses_LPC2000_old
60  * @{
61  */
62 #include "reg_macros.h"
63 #include "nxp_base_addresses.h"
64 /*-------------MCU NUMBER --------------------------------------------------*/
65 /*if MCU has suffix 01 (for ex 2106/01) then is has new VIC and may be other modules */
66 #ifndef i_MCU_MODEL
67  #define i_MCU_MODEL 0
68 #endif
69 /*------ МАКРОСЫ И ОПРЕДЕЛЕНИЯ - MACROSES ------------------------------------*/
70 // Vectored Interrupt Controller Registers (VIC)
71 #if i_MCU_MODEL >= 2300
72  #define VIC_SIZE 32
73 typedef struct
74 {
75  REG32 irqStatus; /**< IRQ Status Register */
76  REG32 fiqStatus; /**< FIQ Status Register */
77  REG32 rawIntr; /**< Raw Interrupt Status Register */
78  REG32 intSelect; /**< Interrupt Select Register */
79  REG32 intEnable; /**< Interrupt Enable Register */
80  REG32 intEnClr; /**< Interrupt Enable Clear Register */
81  REG32 softInt; /**< Software Interrupt Register */
82  REG32 softIntClear; /**< Software Interrupt Clear Register */
83  REG32 protection; /**< Protection Enable Register */
84  REG32 swPrioMask; /**< Software Priority Mask Register */
85  REG32 _pad0[4];
86  REG32 _pad1[50];
87  REG32 vectAddr[VIC_SIZE]; /**< Vector Address Registers */
88  REG32 _pad2[64-VIC_SIZE];
89  REG32 vectCntl[VIC_SIZE]; /**< Vector Control Registers */
90  REG32 _pad3[800];
91  REG32 address; /**< Vector Address Register */
92 } vicRegs_t;
93 #else
94  #define VIC_SIZE 16
95 typedef struct
96 {
97  REG32 irqStatus; /**< IRQ Status Register */
98  REG32 fiqStatus; /**< FIQ Status Register */
99  REG32 rawIntr; /**< Raw Interrupt Status Register */
100  REG32 intSelect; /**< Interrupt Select Register */
101  REG32 intEnable; /**< Interrupt Enable Register */
102  REG32 intEnClr; /**< Interrupt Enable Clear Register */
103  REG32 softInt; /**< Software Interrupt Register */
104  REG32 softIntClr; /**< Software Interrupt Clear Register */
105  REG32 protection; /**< Protection Enable Register */
106  REG32 _pad0[3];
107  REG32 address; /**< Vector Address Register */
108  REG32 defVectAddr; /**< Default Vector Address Register */
109  REG32 _pad1[50];
110 
111  REG32 vectAddr[VIC_SIZE]; /**< Vector Address Registers */
112  REG32 _pad2[64-VIC_SIZE];
113  REG32 vectCntl[VIC_SIZE]; /**< Vector Control Registers */
114 } vicRegs_t;
115 #endif
116 
117 #define VIC_MAX_IRQ_NUMBER (VIC_SIZE-1)
118 
119 #define VIC_HIGHEST_PRIORITY 0x01
120 #define VIC_HIGH_PRIORITY 0x04
121 #define VIC_MEDIUM_PRIORITY 0x07
122 #define VIC_LOW_PRIORITY 0x0B
123 #define VIC_LOWEST_PRIORITY 0x0F
124 
125 
126 // Vectored Interrupt Controller
127 #define VIC ((vicRegs_t *)VIC_BASE)
128 
129 #define IRQn_Type char
130 
131 // VIC Channel Assignments
132 #define VIC_WDT 0
133 #define VIC_ARM_PROGRAMM_INT 2
134 #define VIC_ARM_CORE_ICE_RX 2
135 #define VIC_ARM_CORE_ICE_TX 3
136 #define VIC_TIMER0 4
137 #define VIC_TIMER1 5
138 #define VIC_UART0 6
139 #define VIC_UART1 7
140 #define VIC_PWM 8
141 #define VIC_PWM0 8
142 #define VIC_I2C 9
143 #define VIC_SPI 10
144 #define VIC_SPI0 10
145 #define VIC_SSP0 10
146 #define VIC_SPI1 11
147 #define VIC_SSP1 11
148 #define VIC_PLL 12
149 #define VIC_RTC 13
150 #define VIC_EINT0 14
151 #define VIC_EINT1 15
152 #define VIC_EINT2 16
153 #define VIC_EINT3 17
154 #define VIC_ADC 18
155 #if i_MCU_MODEL >= 2300
156  #define VIC_I2C1 19
157  #define VIC_BOD 20
158  #define VIC_EMAC 21
159  #define VIC_USB 22
160  #define VIC_CAN 23
161  #define VIC_MCI 24
162  #define VIC_DMA 25
163  /* for lpc 24xx*/
164  #define VIC_TIMER2 26
165  #define VIC_TIMER3 27
166  #define VIC_UART2 28
167  #define VIC_UART3 29
168  #define VIC_I2C2 30
169  #define VIC_I2S 31
170 #else
171  #define VIC_CAN1_TX 20
172  #define VIC_CAN2_TX 21
173  #define VIC_CAN3_TX 22
174  #define VIC_CAN4_TX 23
175  #define VIC_RESERVE_23 24
176  #define VIC_RESERVE_24 25
177  #define VIC_CAN1_RX 26
178  #define VIC_CAN2_RX 27
179  #define VIC_CAN3_RX 28
180  #define VIC_CAN4_RX 29
181 #endif
182 
183 
184 
185 
186 
187 // Vector Control Register bit definitions
188 /// Vector Control Register -- Vector Interrupt Controller Enable
189 #define VIC_ENABLE (1 << 5)
190 
191 /// Vector Control Register -- Convert Channel Number to Bit Value
192 #define VIC_BIT(chan) (1 << (chan))
193 
194 #define VICIRQStatus (*(REG32*)(VIC_BASE + 0x000))
195 #define VICFIQStatus (*(REG32*)(VIC_BASE + 0x004))
196 #define VICRawIntr (*(REG32*)(VIC_BASE + 0x008))
197 #define VICIntSelect (*(REG32*)(VIC_BASE + 0x00C))
198 #define VICIntEnable (*(REG32*)(VIC_BASE + 0x010))
199 #define VICIntEnClr (*(REG32*)(VIC_BASE + 0x014))
200 #define VICSoftInt (*(REG32*)(VIC_BASE + 0x018))
201 #define VICSoftIntClr (*(REG32*)(VIC_BASE + 0x01C))
202 #define VICProtection (*(REG32*)(VIC_BASE + 0x020))
203 #define VICSWPrioMask (*(REG32*)(VIC_BASE + 0x024))
204 
205 #define VICVectAddr (*(REG32*)(VIC_BASE + 0xF00))
206 
207 #define VICVectAddr_n(n) (*(REG32*)(VIC_BASE + 256 + n*4))
208 #define VICVectAddr0 VICVectAddr_n(0)
209 #define VICVectAddr1 VICVectAddr_n(1)
210 #define VICVectAddr2 VICVectAddr_n(2)
211 #define VICVectAddr3 VICVectAddr_n(3)
212 #define VICVectAddr4 VICVectAddr_n(4)
213 #define VICVectAddr5 VICVectAddr_n(5)
214 #define VICVectAddr6 VICVectAddr_n(6)
215 #define VICVectAddr7 VICVectAddr_n(7)
216 #define VICVectAddr8 VICVectAddr_n(8)
217 #define VICVectAddr9 VICVectAddr_n(9)
218 #define VICVectAddr10 VICVectAddr_n(10)
219 #define VICVectAddr11 VICVectAddr_n(11)
220 #define VICVectAddr12 VICVectAddr_n(12)
221 #define VICVectAddr13 VICVectAddr_n(13)
222 #define VICVectAddr14 VICVectAddr_n(14)
223 #define VICVectAddr15 VICVectAddr_n(15)
224 #define VICVectAddr16 VICVectAddr_n(16)
225 #define VICVectAddr17 VICVectAddr_n(17)
226 #define VICVectAddr18 VICVectAddr_n(18)
227 #define VICVectAddr19 VICVectAddr_n(19)
228 #define VICVectAddr20 VICVectAddr_n(20)
229 #define VICVectAddr21 VICVectAddr_n(21)
230 #define VICVectAddr22 VICVectAddr_n(22)
231 #define VICVectAddr23 VICVectAddr_n(23)
232 #define VICVectAddr24 VICVectAddr_n(24)
233 #define VICVectAddr25 VICVectAddr_n(25)
234 #define VICVectAddr26 VICVectAddr_n(26)
235 #define VICVectAddr27 VICVectAddr_n(27)
236 #define VICVectAddr28 VICVectAddr_n(28)
237 #define VICVectAddr29 VICVectAddr_n(29)
238 #define VICVectAddr30 VICVectAddr_n(30)
239 #define VICVectAddr31 VICVectAddr_n(31)
240 
241 #define VICVectCntl_n(n) (*(REG32*)(VIC_BASE + 256*2 + n*4))
242 #define VICVectCntl0 VICVectCntl_n(0)
243 #define VICVectCntl1 VICVectCntl_n(1)
244 #define VICVectCntl2 VICVectCntl_n(2)
245 #define VICVectCntl3 VICVectCntl_n(3)
246 #define VICVectCntl4 VICVectCntl_n(4)
247 #define VICVectCntl5 VICVectCntl_n(5)
248 #define VICVectCntl6 VICVectCntl_n(6)
249 #define VICVectCntl7 VICVectCntl_n(7)
250 #define VICVectCntl8 VICVectCntl_n(8)
251 #define VICVectCntl9 VICVectCntl_n(9)
252 #define VICVectCntl10 VICVectCntl_n(10)
253 #define VICVectCntl11 VICVectCntl_n(11)
254 #define VICVectCntl12 VICVectCntl_n(12)
255 #define VICVectCntl13 VICVectCntl_n(13)
256 #define VICVectCntl14 VICVectCntl_n(14)
257 #define VICVectCntl15 VICVectCntl_n(15)
258 #define VICVectCntl16 VICVectCntl_n(16)
259 #define VICVectCntl17 VICVectCntl_n(17)
260 #define VICVectCntl18 VICVectCntl_n(18)
261 #define VICVectCntl19 VICVectCntl_n(19)
262 #define VICVectCntl20 VICVectCntl_n(20)
263 #define VICVectCntl21 VICVectCntl_n(21)
264 #define VICVectCntl22 VICVectCntl_n(22)
265 #define VICVectCntl23 VICVectCntl_n(23)
266 #define VICVectCntl24 VICVectCntl_n(24)
267 #define VICVectCntl25 VICVectCntl_n(25)
268 #define VICVectCntl26 VICVectCntl_n(26)
269 #define VICVectCntl27 VICVectCntl_n(27)
270 #define VICVectCntl28 VICVectCntl_n(28)
271 #define VICVectCntl29 VICVectCntl_n(29)
272 #define VICVectCntl30 VICVectCntl_n(30)
273 #define VICVectCntl31 VICVectCntl_n(31)
274 /*the same*/
275 #define VICVectPriority0 VICVectCntl_n(0)
276 #define VICVectPriority1 VICVectCntl_n(1)
277 #define VICVectPriority2 VICVectCntl_n(2)
278 #define VICVectPriority3 VICVectCntl_n(3)
279 #define VICVectPriority4 VICVectCntl_n(4)
280 #define VICVectPriority5 VICVectCntl_n(5)
281 #define VICVectPriority6 VICVectCntl_n(6)
282 #define VICVectPriority7 VICVectCntl_n(7)
283 #define VICVectPriority8 VICVectCntl_n(8)
284 #define VICVectPriority9 VICVectCntl_n(9)
285 #define VICVectPriority10 VICVectCntl_n(10)
286 #define VICVectPriority11 VICVectCntl_n(11)
287 #define VICVectPriority12 VICVectCntl_n(12)
288 #define VICVectPriority13 VICVectCntl_n(13)
289 #define VICVectPriority14 VICVectCntl_n(14)
290 #define VICVectPriority15 VICVectCntl_n(15)
291 #define VICVectPriority16 VICVectCntl_n(16)
292 #define VICVectPriority17 VICVectCntl_n(17)
293 #define VICVectPriority18 VICVectCntl_n(18)
294 #define VICVectPriority19 VICVectCntl_n(19)
295 #define VICVectPriority20 VICVectCntl_n(20)
296 #define VICVectPriority21 VICVectCntl_n(21)
297 #define VICVectPriority22 VICVectCntl_n(22)
298 #define VICVectPriority23 VICVectCntl_n(23)
299 #define VICVectPriority24 VICVectCntl_n(24)
300 #define VICVectPriority25 VICVectCntl_n(25)
301 #define VICVectPriority26 VICVectCntl_n(26)
302 #define VICVectPriority27 VICVectCntl_n(27)
303 #define VICVectPriority28 VICVectCntl_n(28)
304 #define VICVectPriority29 VICVectCntl_n(29)
305 #define VICVectPriority30 VICVectCntl_n(30)
306 #define VICVectPriority31 VICVectCntl_n(31)
307 
308 #if ((i_MCU_MODEL >= 2100) && (i_MCU_MODEL < 2300))
309  /*----- strange registers--------*/
310  #define VICITCR (*(REG32*)(VIC_BASE + 0x300))
311  #define VICITIP1 (*(REG32*)(VIC_BASE + 0x304))
312  #define VICITIP2 (*(REG32*)(VIC_BASE + 0x308))
313  #define VICITOP1 (*(REG32*)(VIC_BASE + 0x30C))
314  #define VICITOP2 (*(REG32*)(VIC_BASE + 0x310))
315  #define VICPeriphID0 (*(REG32*)(VIC_BASE + 0xFE0))
316  #define VICPeriphID1 (*(REG32*)(VIC_BASE + 0xFE4))
317  #define VICPeriphID2 (*(REG32*)(VIC_BASE + 0xFE8))
318  #define VICPeriphID3 (*(REG32*)(VIC_BASE + 0xFEc))
319 #endif
320 /*-------------System Control Block(SCB)--------------------------------------*/
321 /* System Control Block(SCB) modules include
322  Memory Accelerator Module,
323  Phase Locked Loop,
324  VPB divider,
325  Power Control,
326  External Interrupt,
327  Reset, and
328  Code Security/Debugging
329  */
330 #define SCB_BASE 0xE01FC000
331 
332 /* Memory Accelerator Module (MAM) */
333 #define MAMCR (*(REG32*)(SCB_BASE + 0x000))
334 #define MAMTIM (*(REG32*)(SCB_BASE + 0x004))
335 #define MEMMAP (*(REG32*)(SCB_BASE + 0x040))
336 
337 /* Phase Locked Loop (PLL) */
338 #define PLLCON (*(REG32*)(SCB_BASE + 0x080))
339 #define PLLCFG (*(REG32*)(SCB_BASE + 0x084))
340 #define PLLSTAT (*(REG32*)(SCB_BASE + 0x088))
341 #define PLLFEED (*(REG32*)(SCB_BASE + 0x08C))
342 
343 /* Power Control */
344 #define PCON (*(REG32*)(SCB_BASE + 0x0C0))
345 #define PCONP (*(REG32*)(SCB_BASE + 0x0C4))
346 
347 /** \brief TURN ON PERIPHIRAL MODULE in NXP controller
348  */
349 #define PORT_LPC2XXX_PWR_CONTRL_ON(num) PCONP = PCONP | (1 <<(num##_lpc_periph))
350 #define PORT_LPC2XXX_PWR_CONTRL_OFF(num) PCONP = PCONP & (~(1 <<(num##_lpc_periph)))
351 
352 /* Clock Divider */
353 #define APBDIV (*(REG32*)(SCB_BASE + 0x100))
354 #define CCLKCFG (*(REG32*)(SCB_BASE + 0x104))
355 #define USBCLKCFG (*(REG32*)(SCB_BASE + 0x108))
356 #define CLKSRCSEL (*(REG32*)(SCB_BASE + 0x10C))
357 #define PCLKSEL0 (*(REG32*)(SCB_BASE + 0x1A8))
358 #define PCLKSEL1 (*(REG32*)(SCB_BASE + 0x1AC))
359 
360 /* External Interrupts */
361 #define EXTINT (*(REG32*)(SCB_BASE + 0x140))
362 #define INTWAKE (*(REG32*)(SCB_BASE + 0x144))
363 #define EXTMODE (*(REG32*)(SCB_BASE + 0x148))
364 #define EXTPOLAR (*(REG32*)(SCB_BASE + 0x14C))
365 
366 /* Reset, reset source identification */
367 #define RSID (*(REG32*)(SCB_BASE + 0x180))
368 
369 /* RSID, code security protection */
370 #define CSPR (*(REG32*)(SCB_BASE + 0x184))
371 
372 /* AHB configuration */
373 #define AHBCFG1 (*(REG32*)(SCB_BASE + 0x188))
374 #define AHBCFG2 (*(REG32*)(SCB_BASE + 0x18C))
375 
376 /* System Controls and Status */
377 #define SCS (*(REG32*)(SCB_BASE + 0x1A0))
378 
379 /*-------------TIMERS---------------------------------------------------------*/
380 #define IR_Off 0x00
381 #define TCR_Off 0x04
382 #define TC_Off 0x08
383 #define PR_Off 0x0C
384 #define PC_Off 0x10
385 #define MCR_Off 0x14
386 #define MR0_Off 0x18
387 #define MR1_Off 0x1C
388 #define MR2_Off 0x20
389 #define MR3_Off 0x24
390 #define CCR_Off 0x28
391 #define CR0_Off 0x2C
392 #define CR1_Off 0x30
393 #define CR2_Off 0x34
394 #define CR3_Off 0x38
395 #define EMR_Off 0x3C
396 #define CTCR_Off 0x70
397 
398 #ifndef LPC_T0_BASE
399  #define LPC_T0_BASE LPC_TIM0_BASE
400 #endif
401 #ifndef LPC_T1_BASE
402  #define LPC_T1_BASE LPC_TIM1_BASE
403 #endif
404 #ifndef LPC_T2_BASE
405  #define LPC_T2_BASE LPC_TIM2_BASE
406 #endif
407 #ifndef LPC_T3_BASE
408  #define LPC_T3_BASE LPC_TIM3_BASE
409 #endif
410 
411 #define T0IR VBP_REG32(T0,IR)
412 #define T0TCR VBP_REG32(T0,TCR)
413 #define T0TC VBP_REG32(T0,TC)
414 #define T0PR VBP_REG32(T0,PR)
415 #define T0PC VBP_REG32(T0,PC)
416 #define T0MCR VBP_REG32(T0,MCR)
417 #define T0MR0 VBP_REG32(T0,MR0)
418 #define T0MR1 VBP_REG32(T0,MR1)
419 #define T0MR2 VBP_REG32(T0,MR2)
420 #define T0MR3 VBP_REG32(T0,MR3)
421 #define T0CCR VBP_REG32(T0,CCR)
422 #define T0CR0 VBP_REG32(T0,CR0)
423 #define T0CR1 VBP_REG32(T0,CR1)
424 #define T0CR2 VBP_REG32(T0,CR2)
425 #define T0CR3 VBP_REG32(T0,CR3)
426 #define T0EMR VBP_REG32(T0,EMR)
427 #define T0CTCR VBP_REG32(T0,CTCR)
428 
429 #define T1IR VBP_REG32(T1,IR)
430 #define T1TCR VBP_REG32(T1,TCR)
431 #define T1TC VBP_REG32(T1,TC)
432 #define T1PR VBP_REG32(T1,PR)
433 #define T1PC VBP_REG32(T1,PC)
434 #define T1MCR VBP_REG32(T1,MCR)
435 #define T1MR0 VBP_REG32(T1,MR0)
436 #define T1MR1 VBP_REG32(T1,MR1)
437 #define T1MR2 VBP_REG32(T1,MR2)
438 #define T1MR3 VBP_REG32(T1,MR3)
439 #define T1CCR VBP_REG32(T1,CCR)
440 #define T1CR0 VBP_REG32(T1,CR0)
441 #define T1CR1 VBP_REG32(T1,CR1)
442 #define T1CR2 VBP_REG32(T1,CR2)
443 #define T1CR3 VBP_REG32(T1,CR3)
444 #define T1EMR VBP_REG32(T1,EMR)
445 #define T1CTCR VBP_REG32(T1,CTCR)
446 
447 #define T2IR VBP_REG32(T2,IR)
448 #define T2TCR VBP_REG32(T2,TCR)
449 #define T2TC VBP_REG32(T2,TC)
450 #define T2PR VBP_REG32(T2,PR)
451 #define T2PC VBP_REG32(T2,PC)
452 #define T2MCR VBP_REG32(T2,MCR)
453 #define T2MR0 VBP_REG32(T2,MR0)
454 #define T2MR1 VBP_REG32(T2,MR1)
455 #define T2MR2 VBP_REG32(T2,MR2)
456 #define T2MR3 VBP_REG32(T2,MR3)
457 #define T2CCR VBP_REG32(T2,CCR)
458 #define T2CR0 VBP_REG32(T2,CR0)
459 #define T2CR1 VBP_REG32(T2,CR1)
460 #define T2CR2 VBP_REG32(T2,CR2)
461 #define T2CR3 VBP_REG32(T2,CR3)
462 #define T2EMR VBP_REG32(T2,EMR)
463 #define T2CTCR VBP_REG32(T2,CTCR)
464 
465 #define T3IR VBP_REG32(T3,IR)
466 #define T3TCR VBP_REG32(T3,TCR)
467 #define T3TC VBP_REG32(T3,TC)
468 #define T3PR VBP_REG32(T3,PR)
469 #define T3PC VBP_REG32(T3,PC)
470 #define T3MCR VBP_REG32(T3,MCR)
471 #define T3MR0 VBP_REG32(T3,MR0)
472 #define T3MR1 VBP_REG32(T3,MR1)
473 #define T3MR2 VBP_REG32(T3,MR2)
474 #define T3MR3 VBP_REG32(T3,MR3)
475 #define T3CCR VBP_REG32(T3,CCR)
476 #define T3CR0 VBP_REG32(T3,CR0)
477 #define T3CR1 VBP_REG32(T3,CR1)
478 #define T3CR2 VBP_REG32(T3,CR2)
479 #define T3CR3 VBP_REG32(T3,CR3)
480 #define T3EMR VBP_REG32(T3,EMR)
481 #define T3CTCR VBP_REG32(T3,CTCR)
482 
483 /*-------------Pulse Width Modulator (PWM) -----------------------------------*/
484 /* */
485 #define PWM0IR (*(REG32 *)(LPC_PWM0_BASE + 0x00))
486 #define PWM0TCR (*(REG32 *)(LPC_PWM0_BASE + 0x04))
487 #define PWM0TC (*(REG32 *)(LPC_PWM0_BASE + 0x08))
488 #define PWM0PR (*(REG32 *)(LPC_PWM0_BASE + 0x0C))
489 #define PWM0PC (*(REG32 *)(LPC_PWM0_BASE + 0x10))
490 #define PWM0MCR (*(REG32 *)(LPC_PWM0_BASE + 0x14))
491 #define PWM0MR0 (*(REG32 *)(LPC_PWM0_BASE + 0x18))
492 #define PWM0MR1 (*(REG32 *)(LPC_PWM0_BASE + 0x1C))
493 #define PWM0MR2 (*(REG32 *)(LPC_PWM0_BASE + 0x20))
494 #define PWM0MR3 (*(REG32 *)(LPC_PWM0_BASE + 0x24))
495 #define PWM0CCR (*(REG32 *)(LPC_PWM0_BASE + 0x28))
496 #define PWM0CR0 (*(REG32 *)(LPC_PWM0_BASE + 0x2C))
497 #define PWM0CR1 (*(REG32 *)(LPC_PWM0_BASE + 0x30))
498 #define PWM0CR2 (*(REG32 *)(LPC_PWM0_BASE + 0x34))
499 #define PWM0CR3 (*(REG32 *)(LPC_PWM0_BASE + 0x38))
500 #define PWM0EMR (*(REG32 *)(LPC_PWM0_BASE + 0x3C))
501 #define PWM0MR4 (*(REG32 *)(LPC_PWM0_BASE + 0x40))
502 #define PWM0MR5 (*(REG32 *)(LPC_PWM0_BASE + 0x44))
503 #define PWM0MR6 (*(REG32 *)(LPC_PWM0_BASE + 0x48))
504 #define PWM0PCR (*(REG32 *)(LPC_PWM0_BASE + 0x4C))
505 #define PWM0LER (*(REG32 *)(LPC_PWM0_BASE + 0x50))
506 #define PWM0CTCR (*(REG32 *)(LPC_PWM0_BASE + 0x70))
507 
508 #define PWM1IR (*(REG32 *)(LPC_PWM1_BASE + 0x00))
509 #define PWM1TCR (*(REG32 *)(LPC_PWM1_BASE + 0x04))
510 #define PWM1TC (*(REG32 *)(LPC_PWM1_BASE + 0x08))
511 #define PWM1PR (*(REG32 *)(LPC_PWM1_BASE + 0x0C))
512 #define PWM1PC (*(REG32 *)(LPC_PWM1_BASE + 0x10))
513 #define PWM1MCR (*(REG32 *)(LPC_PWM1_BASE + 0x14))
514 #define PWM1MR0 (*(REG32 *)(LPC_PWM1_BASE + 0x18))
515 #define PWM1MR1 (*(REG32 *)(LPC_PWM1_BASE + 0x1C))
516 #define PWM1MR2 (*(REG32 *)(LPC_PWM1_BASE + 0x20))
517 #define PWM1MR3 (*(REG32 *)(LPC_PWM1_BASE + 0x24))
518 #define PWM1CCR (*(REG32 *)(LPC_PWM1_BASE + 0x28))
519 #define PWM1CR0 (*(REG32 *)(LPC_PWM1_BASE + 0x2C))
520 #define PWM1CR1 (*(REG32 *)(LPC_PWM1_BASE + 0x30))
521 #define PWM1CR2 (*(REG32 *)(LPC_PWM1_BASE + 0x34))
522 #define PWM1CR3 (*(REG32 *)(LPC_PWM1_BASE + 0x38))
523 #define PWM1EMR (*(REG32 *)(LPC_PWM1_BASE + 0x3C))
524 #define PWM1MR4 (*(REG32 *)(LPC_PWM1_BASE + 0x40))
525 #define PWM1MR5 (*(REG32 *)(LPC_PWM1_BASE + 0x44))
526 #define PWM1MR6 (*(REG32 *)(LPC_PWM1_BASE + 0x48))
527 #define PWM1PCR (*(REG32 *)(LPC_PWM1_BASE + 0x4C))
528 #define PWM1LER (*(REG32 *)(LPC_PWM1_BASE + 0x50))
529 #define PWM1CTCR (*(REG32 *)(LPC_PWM1_BASE + 0x70))
530 
531 /*-------------PINS-----------------------------------------------------------*/
532 #define PINSEL_n(n) (*(REG32*)(LPC_PINSEL_BASE + (n<<2))) /**< get PINSEL REG */
533 
534 #define LPC2XXX_PORT0 0
535 #define LPC2XXX_PORT1 1
536 #define LPC2XXX_PORT2 2
537 #define LPC2XXX_PORT3 3
538 #define LPC2XXX_PORT4 4
539 
540 /**
541  *\if russian_lng
542  * Вычислить общий номер ножки согласно номеру порта и ножки
543  *\else
544  * Calculate common pin number accoding to number of port and pin
545  *\endif
546 \code
547  #define UART_1_TX_PIN_NUMBER PORT_PIN_NUMBER(PORT3,16)
548  #define UART_1_RX_PIN_NUMBER PORT_PIN_NUMBER(PORT3,17)
549 \endcode
550  */
551 #define PORT_PIN_NUMBER(prt,number) (prt*32+number)
552 
553 /**
554  *\if russian_lng
555  * Установать вывод ножки номер number согласно value
556  *
557  * P0[0] имеет номер 0, P1[0] имеет номер 32, P2[2] имеет номер 2*32+2=64 и т.д
558  *\else
559  * Set pin accoding to pin number (number) and its mode (value)
560  *
561  * P0[0] has number0, P1[0] has number 32, P2[2] has number 2*32+2=64 and so on
562  *\endif
563 
564 \code
565  PORT_SELECT_PIN (UART_1_TX_PIN_NUMBER, UART_1_TX_PIN_SELECT);
566  PORT_SELECT_PIN (UART_1_RX_PIN_NUMBER, UART_1_RX_PIN_SELECT);
567 \endcode
568  */
569 #define PORT_SELECT_PIN(number,value) PINSEL_n(number>>4) = \
570  (PINSEL_n(number>>4) & (~(3<<((number&0xf)<<1)))) | ((value&3)<<((number&0xf)<<1))
571 
572 /** By default 0 configures GP IO*/
573 #define PORT_PIN_MODE_GPIO 0
574 /*-------------PINS-----------------------------------------------------------*/
575 #define PINSEL0 PINSEL_n(0)
576 #define PINSEL1 PINSEL_n(1)
577 #define PINSEL2 PINSEL_n(2)
578 #define PINSEL3 PINSEL_n(3)
579 #define PINSEL4 PINSEL_n(4)
580 #define PINSEL5 PINSEL_n(5)
581 #define PINSEL6 PINSEL_n(6)
582 #define PINSEL7 PINSEL_n(7)
583 #define PINSEL8 PINSEL_n(8)
584 #define PINSEL9 PINSEL_n(9)
585 #define PINSEL10 PINSEL_n(10)
586 
587 #define PINMODE_n(n) (*(REG32*)(LPC_PINSEL_BASE + 0x40 + (n<<2)))
588 #define PINMODE0 PINMODE_n(0)
589 #define PINMODE1 PINMODE_n(1)
590 #define PINMODE2 PINMODE_n(2)
591 #define PINMODE3 PINMODE_n(3)
592 #define PINMODE4 PINMODE_n(4)
593 #define PINMODE5 PINMODE_n(5)
594 #define PINMODE6 PINMODE_n(6)
595 #define PINMODE7 PINMODE_n(7)
596 #define PINMODE8 PINMODE_n(8)
597 #define PINMODE9 PINMODE_n(9)
598 #define PINMODE10 PINMODE_n(10)
599 
600 #define PINMODE_PULL_UP 0
601 #define PINMODE_DEFAULT PINMODE_PULL_UP
602 #define PINMODE_NO_PULL_ 2
603 #define PINMODE_PULL_DOWN 3
604 
605 
606 /*-------------General Purpose Input/Output (GPIO)----------------------------*/
607 #define GPIO_BASE LPC_GPIO_BASE
608 #define IOPIN0 (*(REG32*)(GPIO_BASE + 0x00))
609 #define IOSET0 (*(REG32*)(GPIO_BASE + 0x04))
610 #define IODIR0 (*(REG32*)(GPIO_BASE + 0x08))
611 #define IOCLR0 (*(REG32*)(GPIO_BASE + 0x0C))
612 #define IOPIN1 (*(REG32*)(GPIO_BASE + 0x10))
613 #define IOSET1 (*(REG32*)(GPIO_BASE + 0x14))
614 #define IODIR1 (*(REG32*)(GPIO_BASE + 0x18))
615 #define IOCLR1 (*(REG32*)(GPIO_BASE + 0x1C))
616 
617 #define IOPIN IOPIN0
618 #define IOSET IOSET0
619 #define IODIR IODIR0
620 #define IOCLR IOCLR0
621 
622 /*-------------GPIO Interrupt Registers --------------------------------------*/
623 #define IO0_INT_EN_R (*(REG32*)(GPIO_BASE + 0x90))
624 #define IO0_INT_EN_F (*(REG32*)(GPIO_BASE + 0x94))
625 #define IO0_INT_STAT_R (*(REG32*)(GPIO_BASE + 0x84))
626 #define IO0_INT_STAT_F (*(REG32*)(GPIO_BASE + 0x88))
627 #define IO0_INT_CLR (*(REG32*)(GPIO_BASE + 0x8C))
628 
629 #define IO2_INT_EN_R (*(REG32*)(GPIO_BASE + 0xB0))
630 #define IO2_INT_EN_F (*(REG32*)(GPIO_BASE + 0xB4))
631 #define IO2_INT_STAT_R (*(REG32*)(GPIO_BASE + 0xA4))
632 #define IO2_INT_STAT_F (*(REG32*)(GPIO_BASE + 0xA8))
633 #define IO2_INT_CLR (*(REG32*)(GPIO_BASE + 0xAC))
634 
635 #define IO_INT_STAT (*(REG32*)(GPIO_BASE + 0x80))
636 
637 #define PARTCFG (*(REG32*)(PARTCFG_BASE + 0x00))
638 /*-------------Fast I/O setup ----------------------------------------------*/
639 #define FIOREG_BASE_ADDR_n(n,off) (*(REG32*)(LPC_FIO_BASE + (n<<5)+ off))
640 #define FIOREG_BASE_ADDR_n16(n,off) (*(REG16*)(LPC_FIO_BASE + (n<<5)+ off))
641 #define FIOREG_BASE_ADDR_n8(n,off) (*(REG8*)(LPC_FIO_BASE + (n<<5)+ off))
642 
643 #define FIO0DIR FIOREG_BASE_ADDR_n(0,0)
644 #define FIO0MASK FIOREG_BASE_ADDR_n(0,0x10)
645 #define FIO0PIN FIOREG_BASE_ADDR_n(0,0x14)
646 #define FIO0SET FIOREG_BASE_ADDR_n(0,0x18)
647 #define FIO0CLR FIOREG_BASE_ADDR_n(0,0x1C)
648 
649 /**FIO DIR CONSTANT TO MAKE PORT BE INPUT*/
650 #define PIN_INPUT 0
651 /**FIO DIR CONSTANT TO MAKE PORT BE OUTPUT*/
652 #define PIN_OUTPUT 1
653 /** SET PIN DIRECTION (PIN_OUTPUT or PIN_INPUT )*/
654 #define PORT_DIRECTION_PIN(number,direction) \
655  FIOREG_BASE_ADDR_n(((number)>>5),0x00) |= 1 << ((number)&0x1F); \
656  if ((number>>6) == 0){ \
657  SCS |= 1;};
658  /* port0 and port1 turning to new scheme*/
659 
660 /** SET PIN TO HIGHT LEVEL (IF DIRECTION IS PIN_OUTPUT )*/
661 #define PORT_SET_PIN(number) \
662  FIOREG_BASE_ADDR_n(((number)>>5),0x18) = 1 << ((number)&0x1F)
663 /** SET PIN TO LOW LEVEL (IF DIRECTION IS PIN_OUTPUT )*/
664 #define PORT_CLEAR_PIN(number) \
665  FIOREG_BASE_ADDR_n(((number)>>5),0x1C) = 1 << ((number)&0x1F)
666 /** GET VALUE OF PIN*/
667 #define PORT_GET_PIN(number) \
668  (FIOREG_BASE_ADDR_n(((number)>>5),0x14) &(1 << ((number)&0x1F)))
669 
670 #define FIO1DIR FIOREG_BASE_ADDR_n(1,0)
671 #define FIO1MASK FIOREG_BASE_ADDR_n(1,0x10)
672 #define FIO1PIN FIOREG_BASE_ADDR_n(1,0x14)
673 #define FIO1SET FIOREG_BASE_ADDR_n(1,0x18)
674 #define FIO1CLR FIOREG_BASE_ADDR_n(1,0x1C)
675 
676 #define FIO2DIR FIOREG_BASE_ADDR_n(2,0)
677 #define FIO2MASK FIOREG_BASE_ADDR_n(2,0x10)
678 #define FIO2PIN FIOREG_BASE_ADDR_n(2,0x14)
679 #define FIO2SET FIOREG_BASE_ADDR_n(2,0x18)
680 #define FIO2CLR FIOREG_BASE_ADDR_n(2,0x1C)
681 
682 #define FIO3DIR FIOREG_BASE_ADDR_n(3,0)
683 #define FIO3MASK FIOREG_BASE_ADDR_n(3,0x10)
684 #define FIO3PIN FIOREG_BASE_ADDR_n(3,0x14)
685 #define FIO3SET FIOREG_BASE_ADDR_n(3,0x18)
686 #define FIO3CLR FIOREG_BASE_ADDR_n(3,0x1C)
687 
688 #define FIO4DIR FIOREG_BASE_ADDR_n(4,0)
689 #define FIO4MASK FIOREG_BASE_ADDR_n(4,0x10)
690 #define FIO4PIN FIOREG_BASE_ADDR_n(4,0x14)
691 #define FIO4SET FIOREG_BASE_ADDR_n(4,0x18)
692 #define FIO4CLR FIOREG_BASE_ADDR_n(4,0x1C)
693 
694 
695 /* FIOs can be accessed throughFIOREG_BASE_ADDR_n8 WORD, HALF-WORD or BYTE. */
696 #define FIO0DIR0 FIOREG_BASE_ADDR_n8(0,0)
697 #define FIO1DIR0 FIOREG_BASE_ADDR_n8(1,0)
698 #define FIO2DIR0 FIOREG_BASE_ADDR_n8(2,0)
699 #define FIO3DIR0 FIOREG_BASE_ADDR_n8(3,0)
700 #define FIO4DIR0 FIOREG_FIOREG_BASE_ADDR_n8BASE_ADDR_n8(4,0)
701 
702 #define FIO0DIR1 FIOREG_BASE_ADDR_n8(0,1)
703 #define FIO1DIR1 FIOREG_BASE_ADDR_n8(1,1)
704 #define FIO2DIR1 FIOREG_BASE_ADDR_n8(2,1)
705 #define FIO3DIR1 FIOREG_BASE_ADDR_n8(3,1)
706 #define FIO4DIR1 FIOREG_BASE_ADDR_n8(4,1)
707 
708 #define FIO0DIR2 FIOREG_BASE_ADDR_n8(0,2)
709 #define FIO1DIR2 FIOREG_BASE_ADDR_n8(1,2)
710 #define FIO2DIR2 FIOREG_BASE_ADDR_n8(2,2)
711 #define FIO3DIR2 FIOREG_BASE_ADDR_n8(3,2)
712 #define FIO4DIR2 FIOREG_BASE_ADDR_n8(4,2)
713 
714 #define FIO0DIR3 FIOREG_BASE_ADDR_n8(0,3)
715 #define FIO1DIR3 FIOREG_BASE_ADDR_n8(1,3)
716 #define FIO2DIR3 FIOREG_BASE_ADDR_n8(2,3)
717 #define FIO3DIR3 FIOREG_BASE_ADDR_n8(3,3)
718 #define FIO4DIR3 FIOREG_BASE_ADDR_n8(4,3)
719 
720 #define FIO0DIRL FIOREG_BASE_ADDR_n16(0,0)
721 #define FIO1DIRL FIOREG_BASE_ADDR_n16(1,0)
722 #define FIO2DIRL FIOREG_BASE_ADDR_n16(2,0)
723 #define FIO3DIRL FIOREG_BASE_ADDR_n16(3,0)
724 #define FIO4DIRL FIOREG_BASE_ADDR_n16(4,0)
725 
726 #define FIO0DIRU FIOREG_BASE_ADDR_n16(0,2)
727 #define FIO1DIRU FIOREG_BASE_ADDR_n16(1,2)
728 #define FIO2DIRU FIOREG_BASE_ADDR_n16(2,2)
729 #define FIO3DIRU FIOREG_BASE_ADDR_n16(3,2)
730 #define FIO4DIRU FIOREG_BASE_ADDR_n16(4,2)
731 /*-----------------*/
732 #define FIOREG_BASE_ADDR_n8_FIOMASK(letter1,letter2) \
733  FIOREG_BASE_ADDR_n8(letter1,0x10+letter2)
734 
735 #define FIO0MASK0 FIOREG_BASE_ADDR_n8_FIOMASK(0,0)
736 #define FIO1MASK0 FIOREG_BASE_ADDR_n8_FIOMASK(1,0)
737 #define FIO2MASK0 FIOREG_BASE_ADDR_n8_FIOMASK(2,0)
738 #define FIO3MASK0 FIOREG_BASE_ADDR_n8_FIOMASK(3,0)
739 #define FIO4MASK0 FIOREG_BASE_ADDR_n8_FIOMASK(4,0)
740 
741 #define FIO0MASK1 FIOREG_BASE_ADDR_n8_FIOMASK(0,1)
742 #define FIO1MASK1 FIOREG_BASE_ADDR_n8_FIOMASK(1,1)
743 #define FIO2MASK1 FIOREG_BASE_ADDR_n8_FIOMASK(2,1)
744 #define FIO3MASK1 FIOREG_BASE_ADDR_n8_FIOMASK(3,1)
745 #define FIO4MASK1 FIOREG_BASE_ADDR_n8_FIOMASK(4,1)
746 
747 #define FIO0MASK2 FIOREG_BASE_ADDR_n8_FIOMASK(0,2)
748 #define FIO1MASK2 FIOREG_BASE_ADDR_n8_FIOMASK(1,2)
749 #define FIO2MASK2 FIOREG_BASE_ADDR_n8_FIOMASK(2,2)
750 #define FIO3MASK2 FIOREG_BASE_ADDR_n8_FIOMASK(3,2)
751 #define FIO4MASK2 FIOREG_BASE_ADDR_n8_FIOMASK(4,2)
752 
753 #define FIO0MASK3 FIOREG_BASE_ADDR_n8_FIOMASK(0,3)
754 #define FIO1MASK3 FIOREG_BASE_ADDR_n8_FIOMASK(1,3)
755 #define FIO2MASK3 FIOREG_BASE_ADDR_n8_FIOMASK(2,3)
756 #define FIO3MASK3 FIOREG_BASE_ADDR_n8_FIOMASK(3,3)
757 #define FIO4MASK3 FIOREG_BASE_ADDR_n8_FIOMASK(4,3)
758 /*-----------------*/
759 #define FIOREG_BASE_ADDR_n16_FIOMASKL(letter1) \
760  FIOREG_BASE_ADDR_n16(letter1,0x10)
761 
762 #define FIOREG_BASE_ADDR_n16_FIOMASKU(letter1) \
763  FIOREG_BASE_ADDR_n16(letter1,0x12)
764 
765 #define FIO0MASKL FIOREG_BASE_ADDR_n16_FIOMASKL(0)
766 #define FIO1MASKL FIOREG_BASE_ADDR_n16_FIOMASKL(1)
767 #define FIO2MASKL FIOREG_BASE_ADDR_n16_FIOMASKL(2)
768 #define FIO3MASKL FIOREG_BASE_ADDR_n16_FIOMASKL(3)
769 #define FIO4MASKL FIOREG_BASE_ADDR_n16_FIOMASKL(4)
770 
771 #define FIO0MASKU FIOREG_BASE_ADDR_n16_FIOMASKU(0)
772 #define FIO1MASKU FIOREG_BASE_ADDR_n16_FIOMASKU(1)
773 #define FIO2MASKU FIOREG_BASE_ADDR_n16_FIOMASKU(2)
774 #define FIO3MASKU FIOREG_BASE_ADDR_n16_FIOMASKU(3)
775 #define FIO4MASKU FIOREG_BASE_ADDR_n16_FIOMASKU(4)
776 /*-----------------*/ /*-----------------*/
777 #define FIO_BASE LPC_FIO_BASE
778 #define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE + 0x14))
779 #define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE + 0x34))
780 #define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE + 0x54))
781 #define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE + 0x74))
782 #define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE + 0x94))
783 
784 #define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE + 0x15))
785 #define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE + 0x35))
786 #define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE + 0x55))
787 #define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE + 0x75))
788 #define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE + 0x95))
789 
790 #define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE + 0x16))
791 #define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE + 0x36))
792 #define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE + 0x56))
793 #define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE + 0x76))
794 #define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE + 0x96))
795 
796 #define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE + 0x17))
797 #define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE + 0x37))
798 #define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE + 0x57))
799 #define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE + 0x77))
800 #define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE + 0x97))
801 
802 #define FIO0PINL (*(volatile unsigned short *)(FIO_BASE + 0x14))
803 #define FIO1PINL (*(volatile unsigned short *)(FIO_BASE + 0x34))
804 #define FIO2PINL (*(volatile unsigned short *)(FIO_BASE + 0x54))
805 #define FIO3PINL (*(volatile unsigned short *)(FIO_BASE + 0x74))
806 #define FIO4PINL (*(volatile unsigned short *)(FIO_BASE + 0x94))
807 
808 #define FIO0PINU (*(volatile unsigned short *)(FIO_BASE + 0x16))
809 #define FIO1PINU (*(volatile unsigned short *)(FIO_BASE + 0x36))
810 #define FIO2PINU (*(volatile unsigned short *)(FIO_BASE + 0x56))
811 #define FIO3PINU (*(volatile unsigned short *)(FIO_BASE + 0x76))
812 #define FIO4PINU (*(volatile unsigned short *)(FIO_BASE + 0x96))
813 
814 #define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE + 0x18))
815 #define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE + 0x38))
816 #define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE + 0x58))
817 #define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE + 0x78))
818 #define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE + 0x98))
819 
820 #define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE + 0x19))
821 #define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE + 0x29))
822 #define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE + 0x59))
823 #define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE + 0x79))
824 #define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE + 0x99))
825 
826 #define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE + 0x1A))
827 #define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE + 0x3A))
828 #define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE + 0x5A))
829 #define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE + 0x7A))
830 #define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE + 0x9A))
831 
832 #define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE + 0x1B))
833 #define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE + 0x3B))
834 #define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE + 0x5B))
835 #define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE + 0x7B))
836 #define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE + 0x9B))
837 
838 #define FIO0SETL (*(volatile unsigned short *)(FIO_BASE + 0x18))
839 #define FIO1SETL (*(volatile unsigned short *)(FIO_BASE + 0x38))
840 #define FIO2SETL (*(volatile unsigned short *)(FIO_BASE + 0x58))
841 #define FIO3SETL (*(volatile unsigned short *)(FIO_BASE + 0x78))
842 #define FIO4SETL (*(volatile unsigned short *)(FIO_BASE + 0x98))
843 
844 #define FIO0SETU (*(volatile unsigned short *)(FIO_BASE + 0x1A))
845 #define FIO1SETU (*(volatile unsigned short *)(FIO_BASE + 0x3A))
846 #define FIO2SETU (*(volatile unsigned short *)(FIO_BASE + 0x5A))
847 #define FIO3SETU (*(volatile unsigned short *)(FIO_BASE + 0x7A))
848 #define FIO4SETU (*(volatile unsigned short *)(FIO_BASE + 0x9A))
849 
850 #define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE + 0x1C))
851 #define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE + 0x3C))
852 #define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE + 0x5C))
853 #define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE + 0x7C))
854 #define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE + 0x9C))
855 
856 #define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE + 0x1D))
857 #define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE + 0x2D))
858 #define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE + 0x5D))
859 #define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE + 0x7D))
860 #define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE + 0x9D))
861 
862 #define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE + 0x1E))
863 #define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE + 0x3E))
864 #define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE + 0x5E))
865 #define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE + 0x7E))
866 #define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE + 0x9E))
867 
868 #define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE + 0x1F))
869 #define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE + 0x3F))
870 #define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE + 0x5F))
871 #define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE + 0x7F))
872 #define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE + 0x9F))
873 
874 #define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE + 0x1E))
875 #define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE + 0x3E))
876 #define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE + 0x5E))
877 #define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE + 0x7E))
878 #define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE + 0x9E))
879 
880 /* \todo Migrating to the LPC2300/2400 family
881 The following key improvements have been done to the VIC:
882 1. VIC register accesses are now controlled by software using the Protection Enable
883 register (VICProtection-0xFFFF F020). This register is accessible only in an ARM
884 privileged mode.
885 2. The VICAddress register resides in a new location in memory, i.e. 0xFFFF FF00.
886 Hence the IRQ interrupt vector (residing at 0x18) should now be modified as:
887  LDR PC, [PC, # -0x0120]
888  Previously, the instruction would be:
889  LDR PC, [PC, # -0x0FF0]
890 3. Spurious interrupts can no longer occur in the LPC23xx/LPC24xx. Hence the Default
891 Address Register is no longer available in this family.
892  */
893 /*------Universal Asynchronous Receiver PINS (UART0)--------------------------*/
894 #ifndef UART_0_TX_PIN_NUMBER
895 #if i_MCU_MODEL >= 2300
896  #define UART_0_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,2)/**< PINSEL0 Mask for UART0 */
897 #else
898  #define UART_0_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,0)/**< PINSEL0 Mask for UART0 */
899 
900 #endif
901 #endif
902 #ifndef UART_0_RX_PIN_NUMBER
903 #define UART_0_RX_PIN_NUMBER (UART_0_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART0*/
904 #endif
905 #ifndef UART_0_TX_PIN_SELECT
906 #define UART_0_TX_PIN_SELECT 1 /**<PINSEL0 Value for UART0*/
907 #endif
908 #ifndef UART_0_RX_PIN_SELECT
909 #define UART_0_RX_PIN_SELECT UART_0_TX_PIN_SELECT /**<PINSEL0 Value for UART0*/
910 #endif
911 
912 #ifndef UART_1_TX_PIN_NUMBER
913 #if i_MCU_MODEL >= 2300
914  #define UART_1_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,10)/**< PINSEL0 Mask for UART1*/
915 #else
916  #define UART_1_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,8)/**< PINSEL0 Mask for UART1*/
917 
918 #endif
919 #endif
920 
921 #ifndef UART_1_RX_PIN_NUMBER
922 #define UART_1_RX_PIN_NUMBER (UART_1_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART1*/
923 #endif
924 #ifndef UART_1_TX_PIN_SELECT
925 #define UART_1_TX_PIN_SELECT 1 /**<PINSEL0 Value for UART1*/
926 #endif
927 #ifndef UART_1_RX_PIN_SELECT
928 #define UART_1_RX_PIN_SELECT UART_1_TX_PIN_SELECT /**<PINSEL0 Value for UART1*/
929 #endif
930 #if i_MCU_MODEL >= 2300
931 #ifndef UART_2_TX_PIN_NUMBER
932  #define UART_2_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,10)/**< PINSEL0 Mask*/
933 #endif
934 #ifndef UART_2_RX_PIN_NUMBER
935  #define UART_2_RX_PIN_NUMBER (UART_2_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART0*/
936 #endif
937 #ifndef UART_2_TX_PIN_SELECT
938  #define UART_2_TX_PIN_SELECT 1 /**<PINSEL Value for UART1*/
939 #endif
940 #ifndef UART_2_RX_PIN_SELECT
941  #define UART_2_RX_PIN_SELECT UART_2_TX_PIN_SELECT /**<PINSEL0 Value for UART1*/
942 #endif
943 
944 #ifndef UART_3_TX_PIN_NUMBER
945  #define UART_3_TX_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,25)/**< PINSEL0 Mask*/
946 #endif
947 #ifndef UART_3_RX_PIN_NUMBER
948  #define UART_3_RX_PIN_NUMBER (UART_3_TX_PIN_NUMBER+1)/**<PINSEL0 Mask for UART0*/
949 #endif
950 #ifndef UART_3_TX_PIN_SELECT
951  #define UART_3_TX_PIN_SELECT 3 /**<PINSEL Value for UART1*/
952 #endif
953 #ifndef UART_3_RX_PIN_SELECT
954  #define UART_3_RX_PIN_SELECT UART_3_TX_PIN_SELECT /**<PINSEL0 Value for UART1*/
955 #endif
956 
957 
958 /*------Universal Asynchronous Receiver Transmitter 0 (UART0)-----------------*/
959 #define UART01_BASE_ADDR(n,off) (*(REG32*)(LPC_UART0_BASE + n*0x4000+ off))
960 #define UART23_BASE_ADDR(n,off) (*(REG32*)(LPC_UART2_BASE + (n-2)*0x4000+ off))
961 /* can do more complex macrising*/
962 #define U0RBR UART01_BASE_ADDR(0,0x00)
963 #define U0THR UART01_BASE_ADDR(0,0x00)
964 #define U0DLL UART01_BASE_ADDR(0,0x00)
965 #define U0DLM UART01_BASE_ADDR(0,0x04)
966 #define U0IER UART01_BASE_ADDR(0,0x04)
967 #define U0IIR UART01_BASE_ADDR(0,0x08)
968 #define U0FCR UART01_BASE_ADDR(0,0x08)
969 #define U0LCR UART01_BASE_ADDR(0,0x0C)
970 #define U0LSR UART01_BASE_ADDR(0,0x14)
971 #define U0SCR UART01_BASE_ADDR(0,0x1C)
972 #define U0ACR UART01_BASE_ADDR(0,0x20)
973 #define U0ICR UART01_BASE_ADDR(0,0x24)
974 #define U0FDR UART01_BASE_ADDR(0,0x28)
975 #define U0TER UART01_BASE_ADDR(0,0x30)
976 /*------Universal Asynchronous Receiver Transmitter 1 (UART0)-----------------*/
977 #define U1RBR UART01_BASE_ADDR(1,0x00)
978 #define U1THR UART01_BASE_ADDR(1,0x00)
979 #define U1DLL UART01_BASE_ADDR(1,0x00)
980 #define U1DLM UART01_BASE_ADDR(1,0x04)
981 #define U1IER UART01_BASE_ADDR(1,0x04)
982 #define U1IIR UART01_BASE_ADDR(1,0x08)
983 #define U1FCR UART01_BASE_ADDR(1,0x08)
984 #define U1LCR UART01_BASE_ADDR(1,0x0C)
985 #define U1MCR UART01_BASE_ADDR(1,0x10) /* only UART1*/
986 #define U1LSR UART01_BASE_ADDR(1,0x14)
987 #define U1MSR UART01_BASE_ADDR(1,0x18) /* only UART1*/
988 #define U1SCR UART01_BASE_ADDR(1,0x1C)
989 #define U1ACR UART01_BASE_ADDR(1,0x20)
990 #define U1ICR UART01_BASE_ADDR(1,0x24)
991 #define U1FDR UART01_BASE_ADDR(1,0x28)
992 #define U1TER UART01_BASE_ADDR(1,0x30)
993 /*------Universal Asynchronous Receiver Transmitter 2 (UART0)-----------------*/
994 #define U2RBR UART23_BASE_ADDR(2,0x00)
995 #define U2THR UART23_BASE_ADDR(2,0x00)
996 #define U2DLL UART23_BASE_ADDR(2,0x00)
997 #define U2DLM UART23_BASE_ADDR(2,0x04)
998 #define U2IER UART23_BASE_ADDR(2,0x04)
999 #define U2IIR UART23_BASE_ADDR(2,0x08)
1000 #define U2FCR UART23_BASE_ADDR(2,0x08)
1001 #define U2LCR UART23_BASE_ADDR(2,0x0C)
1002 #define U2LSR UART23_BASE_ADDR(2,0x14)
1003 #define U2SCR UART23_BASE_ADDR(2,0x1C)
1004 #define U2ACR UART23_BASE_ADDR(2,0x20)
1005 #define U2ICR UART23_BASE_ADDR(2,0x24)
1006 #define U2FDR UART23_BASE_ADDR(2,0x28)
1007 #define U2TER UART23_BASE_ADDR(2,0x30)
1008 /*------Universal Asynchronous Receiver Transmitter 3 (UART0)-----------------*/
1009 #define U3RBR UART23_BASE_ADDR(3,0x00)
1010 #define U3THR UART23_BASE_ADDR(3,0x00)
1011 #define U3DLL UART23_BASE_ADDR(3,0x00)
1012 #define U3DLM UART23_BASE_ADDR(3,0x04)
1013 #define U3IER UART23_BASE_ADDR(3,0x04)
1014 #define U3IIR UART23_BASE_ADDR(3,0x08)
1015 #define U3FCR UART23_BASE_ADDR(3,0x08)
1016 #define U3LCR UART23_BASE_ADDR(3,0x0C)
1017 #define U3LSR UART23_BASE_ADDR(3,0x14)
1018 #define U3SCR UART23_BASE_ADDR(3,0x1C)
1019 #define U3ACR UART23_BASE_ADDR(3,0x20)
1020 #define U3ICR UART23_BASE_ADDR(3,0x24)
1021 #define U3FDR UART23_BASE_ADDR(3,0x28)
1022 #define U3TER UART23_BASE_ADDR(3,0x30)
1023 
1024 /*------I2C Interface 0 (I2C0)------------------------------------------------*/
1025 #define I20CONSET (*(REG32*)(LPC_I2C0_BASE + 0x00))
1026 #define I20STAT (*(REG32*)(LPC_I2C0_BASE + 0x04))
1027 #define I20DAT (*(REG32*)(LPC_I2C0_BASE + 0x08))
1028 #define I20ADR (*(REG32*)(LPC_I2C0_BASE + 0x0C))
1029 #define I20SCLH (*(REG32*)(LPC_I2C0_BASE + 0x10))
1030 #define I20SCLL (*(REG32*)(LPC_I2C0_BASE + 0x14))
1031 #define I20CONCLR (*(REG32*)(LPC_I2C0_BASE + 0x18))
1032 //Slightly different naming
1033 #define I2C0CONSET I20CONSET
1034 #define I2C0STAT I20STAT
1035 #define I2C0DAT I20DAT
1036 #define I2C0ADR I20ADR
1037 #define I2C0SCLH I20SCLH
1038 #define I2C0SCLL I20SCLL
1039 #define I2C0CONCLR I20CONCLR
1040 
1041 /*------I2C Interface 1 (I2C1)------------------------------------------------*/
1042 #define I21CONSET (*(REG32*)(LPC_I2C1_BASE + 0x00))
1043 #define I21STAT (*(REG32*)(LPC_I2C1_BASE + 0x04))
1044 #define I21DAT (*(REG32*)(LPC_I2C1_BASE + 0x08))
1045 #define I21ADR (*(REG32*)(LPC_I2C1_BASE + 0x0C))
1046 #define I21SCLH (*(REG32*)(LPC_I2C1_BASE + 0x10))
1047 #define I21SCLL (*(REG32*)(LPC_I2C1_BASE + 0x14))
1048 #define I21CONCLR (*(REG32*)(LPC_I2C1_BASE + 0x18))
1049 /*------I2C Interface 2 (I2C2)------------------------------------------------*/
1050 #define I22CONSET (*(REG32*)(LPC_I2C2_BASE + 0x00))
1051 #define I22STAT (*(REG32*)(LPC_I2C2_BASE + 0x04))
1052 #define I22DAT (*(REG32*)(LPC_I2C2_BASE + 0x08))
1053 #define I22ADR (*(REG32*)(LPC_I2C2_BASE + 0x0C))
1054 #define I22SCLH (*(REG32*)(LPC_I2C2_BASE + 0x10))
1055 #define I22SCLL (*(REG32*)(LPC_I2C2_BASE + 0x14))
1056 #define I22CONCLR (*(REG32*)(LPC_I2C2_BASE + 0x18))
1057 /*------SPI0 (Serial Peripheral Interface 0) ---------------------------------*/
1058 #if i_MCU_MODEL >= 2300
1059  #ifndef SPI_0_SCK_PIN_NUMBER
1060  #define SPI_0_SCK_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,15)/**< PINSEL0 Mask for SPI */
1061  #endif
1062  #ifndef SPI_0_SEL_PIN_NUMBER
1063  #define SPI_0_SEL_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 1)
1064  #endif
1065  #ifndef SPI_0_MISO_PIN_NUMBER
1066  #define SPI_0_MISO_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 2)
1067  #endif
1068  #ifndef SPI_0_ALL_PIN_SELECT
1069  #define SPI_0_ALL_PIN_SELECT 3
1070  #endif
1071  #ifndef SSP_0_ALL_PIN_SELECT
1072  #define SSP_0_ALL_PIN_SELECT 2
1073  #endif
1074 #else /* i_MCU_MODEL >= 2300*/
1075  #ifndef SPI_0_ALL_PIN_SELECT
1076  #define SPI_0_ALL_PIN_SELECT 2
1077  #endif
1078 
1079  #ifndef SPI_0_SCK_PIN_NUMBER
1080  #define SPI_0_SCK_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,4)
1081  #endif
1082  #ifndef SPI_0_MISO_PIN_NUMBER
1083  #define SPI_0_MISO_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 1)
1084  #endif
1085  #ifndef SPI_0_SEL_PIN_NUMBER
1086  #define SPI_0_SEL_PIN_NUMBER (SPI_0_SCK_PIN_NUMBER + 3)
1087  #endif
1088 
1089 
1090  #endif
1091  #ifndef SPI_0_MOSI_PIN_NUMBER
1092  #define SPI_0_MOSI_PIN_NUMBER (SPI_0_MISO_PIN_NUMBER + 1) /* always after MISO*/
1093  #endif
1094 #endif
1095 
1096 
1097 #define S0SPCR (*(REG32*)(LPC_SPI0_BASE + 0x00))
1098 #define S0SPSR (*(REG32*)(LPC_SPI0_BASE + 0x04))
1099 #define S0SPDR (*(REG32*)(LPC_SPI0_BASE + 0x08))
1100 #define S0SPCCR (*(REG32*)(LPC_SPI0_BASE + 0x0C))
1101 #define S0SPTCR (*(REG32*)(LPC_SPI0_BASE + 0x10)) //SPI Test Control Register ??
1102 #define S0SPTSR (*(REG32*)(LPC_SPI0_BASE + 0x14)) //SPI Test Status Register ??
1103 #define S0SPINT (*(REG32*)(LPC_SPI0_BASE + 0x1C))
1104 /*------ SSP0 Controller-------------------- ---------------------------------*/
1105 #define SSP0CR0 (*(REG32*)(LPC_SSP0_BASE + 0x00))
1106 #define SSP0CR1 (*(REG32*)(LPC_SSP0_BASE + 0x04))
1107 #define SSP0DR (*(REG32*)(LPC_SSP0_BASE + 0x08))
1108 #define SSP0SR (*(REG32*)(LPC_SSP0_BASE + 0x0C))
1109 #define SSP0CPSR (*(REG32*)(LPC_SSP0_BASE + 0x10))
1110 #define SSP0IMSC (*(REG32*)(LPC_SSP0_BASE + 0x14))
1111 #define SSP0RIS (*(REG32*)(LPC_SSP0_BASE + 0x18))
1112 #define SSP0MIS (*(REG32*)(LPC_SSP0_BASE + 0x1C))
1113 #define SSP0ICR (*(REG32*)(LPC_SSP0_BASE + 0x20))
1114 #define SSP0DMACR (*(REG32*)(LPC_SSP0_BASE + 0x24))
1115 /*------------------------------------*/
1116 #if i_MCU_MODEL >= 2300
1117  #ifndef SSP_1_SCK_PIN_NUMBER
1118  #define SSP_1_SCK_PIN_NUMBER PORT_PIN_NUMBER(LPC2XXX_PORT0,7)/**< PINSEL0 Mask for SPI */
1119  #endif
1120  #ifndef SSP_1_SEL_PIN_NUMBER
1121  #define SSP_1_SEL_PIN_NUMBER (SSP_1_SCK_PIN_NUMBER - 1)
1122  #endif
1123  #ifndef SSP_1_MISO_PIN_NUMBER
1124  #define SSP_1_MISO_PIN_NUMBER (SSP_1_SCK_PIN_NUMBER + 1)
1125  #endif
1126  #ifndef SSP_1_MOSI_PIN_NUMBER
1127  #define SSP_1_MOSI_PIN_NUMBER (SSP_1_SCK_PIN_NUMBER + 2)
1128  #endif
1129  #ifndef SSP_1_ALL_PIN_SELECT
1130  #define SSP_1_ALL_PIN_SELECT 2
1131  #endif
1132 /*------ SSP1 Controller-------------------- ---------------------------------*/
1133 #define SSP1CR0 (*(REG32*)(LPC_SSP1_BASE + 0x00))
1134 #define SSP1CR1 (*(REG32*)(LPC_SSP1_BASE + 0x04))
1135 #define SSP1DR (*(REG32*)(LPC_SSP1_BASE + 0x08))
1136 #define SSP1SR (*(REG32*)(LPC_SSP1_BASE + 0x0C))
1137 #define SSP1CPSR (*(REG32*)(LPC_SSP1_BASE + 0x10))
1138 #define SSP1IMSC (*(REG32*)(LPC_SSP1_BASE + 0x14))
1139 #define SSP1RIS (*(REG32*)(LPC_SSP1_BASE + 0x18))
1140 #define SSP1MIS (*(REG32*)(LPC_SSP1_BASE + 0x1C))
1141 #define SSP1ICR (*(REG32*)(LPC_SSP1_BASE + 0x20))
1142 #define SSP1DMACR (*(REG32*)(LPC_SSP1_BASE + 0x24))
1143 #endif /*i_MCU_MODEL*/
1144 
1145 /*-------------- Real Time Clock --------------------------------------------*/
1146 /* ---- RTC: Miscellaneous Register Group ------------------ */
1147 #define RTC_ILR (*(REG32*)(LPC_RTC_BASE + 0x00))
1148 #define RTC_CTC (*(REG32*)(LPC_RTC_BASE + 0x04))
1149 #define RTC_CCR (*(REG32*)(LPC_RTC_BASE + 0x08))
1150 #define RTC_CIIR (*(REG32*)(LPC_RTC_BASE + 0x0C))
1151 #define RTC_AMR (*(REG32*)(LPC_RTC_BASE + 0x10))
1152 #define RTC_CTIME0 (*(REG32*)(LPC_RTC_BASE + 0x14))
1153 #define RTC_CTIME1 (*(REG32*)(LPC_RTC_BASE + 0x18))
1154 #define RTC_CTIME2 (*(REG32*)(LPC_RTC_BASE + 0x1C))
1155 
1156 /* ---- RTC: Timer Control Group --------------------------- */
1157 #define RTC_SEC (*(REG32*)(LPC_RTC_BASE + 0x20))
1158 #define RTC_MIN (*(REG32*)(LPC_RTC_BASE + 0x24))
1159 #define RTC_HOUR (*(REG32*)(LPC_RTC_BASE + 0x28))
1160 #define RTC_DOM (*(REG32*)(LPC_RTC_BASE + 0x2C))
1161 #define RTC_DOW (*(REG32*)(LPC_RTC_BASE + 0x30))
1162 #define RTC_DOY (*(REG32*)(LPC_RTC_BASE + 0x34))
1163 #define RTC_MONTH (*(REG32*)(LPC_RTC_BASE + 0x38))
1164 #define RTC_YEAR (*(REG32*)(LPC_RTC_BASE + 0x3C))
1165 #define RTC_CISS (*(REG32*)(LPC_RTC_BASE + 0x40))
1166 
1167 /* ---- RTC: Alarm Control Group --------------------------- */
1168 #define RTC_ALSEC (*(REG32*)(LPC_RTC_BASE + 0x60))
1169 #define RTC_ALMIN (*(REG32*)(LPC_RTC_BASE + 0x64))
1170 #define RTC_ALHOUR (*(REG32*)(LPC_RTC_BASE + 0x68))
1171 #define RTC_ALDOM (*(REG32*)(LPC_RTC_BASE + 0x6C))
1172 #define RTC_ALDOW (*(REG32*)(LPC_RTC_BASE + 0x70))
1173 #define RTC_ALDOY (*(REG32*)(LPC_RTC_BASE + 0x74))
1174 #define RTC_ALMON (*(REG32*)(LPC_RTC_BASE + 0x78))
1175 #define RTC_ALYEAR (*(REG32*)(LPC_RTC_BASE + 0x7C))
1176 /* ---- RTC: Reference Clock Divider Group ----------------- */
1177 #define RTC_PREINT (*(REG32*)(LPC_RTC_BASE + 0x80))
1178 #define RTC_PREFRAC (*(REG32*)(LPC_RTC_BASE + 0x84))
1179 /*------------------------ A/D Converter 0 (AD0) -----------------------------*/
1180 #define AD0CR (*(REG32*)(LPC_AD0_BASE + 0x00))
1181 #define AD0GDR (*(REG32*)(LPC_AD0_BASE + 0x04))
1182 #define AD0INTEN (*(REG32*)(LPC_AD0_BASE + 0x0C))
1183 #define AD0DR0 (*(REG32*)(LPC_AD0_BASE + 0x10))
1184 #define AD0DR1 (*(REG32*)(LPC_AD0_BASE + 0x14))
1185 #define AD0DR2 (*(REG32*)(LPC_AD0_BASE + 0x18))
1186 #define AD0DR3 (*(REG32*)(LPC_AD0_BASE + 0x1C))
1187 #define AD0DR4 (*(REG32*)(LPC_AD0_BASE + 0x20))
1188 #define AD0DR5 (*(REG32*)(LPC_AD0_BASE + 0x24))
1189 #define AD0DR6 (*(REG32*)(LPC_AD0_BASE + 0x28))
1190 #define AD0DR7 (*(REG32*)(LPC_AD0_BASE + 0x2C))
1191 #define AD0STAT (*(REG32*)(LPC_AD0_BASE + 0x30))
1192 
1193 
1194 /*-------------------------------- D/A Converter -----------------------------*/
1195 #define DACR (*(REG32*)(LPC_DAC_BASE + 0x0))
1196 /*-------------------------------- Watchdog-----------------------------*/
1197 #define WDMOD (*(REG32*)(LPC_WDG_BASE + 0x0))
1198 #define WDTC (*(REG32*)(LPC_WDG_BASE + 0x04))
1199 #define WDFEED (*(REG32*)(LPC_WDG_BASE + 0x08))
1200 #define WDTV (*(REG32*)(LPC_WDG_BASE + 0x0C))
1201 #define WDCLKSEL (*(REG32*)(LPC_WDG_BASE + 0x10))
1202 
1203 /*-------------- Ethernet ----------------------------------------------------*/
1204 #define MAC_MAC1 (*(REG32*)(LPC_MAC_BASE + 0x000)) /* MAC config reg 1 */
1205 #define MAC_MAC2 (*(REG32*)(LPC_MAC_BASE + 0x004)) /* MAC config reg 2 */
1206 #define MAC_IPGT (*(REG32*)(LPC_MAC_BASE + 0x008)) /* b2b InterPacketGap reg */
1207 #define MAC_IPGR (*(REG32*)(LPC_MAC_BASE + 0x00C)) /* non b2b InterPacketGap reg */
1208 #define MAC_CLRT (*(REG32*)(LPC_MAC_BASE + 0x010)) /* CoLlision window/ReTry reg */
1209 #define MAC_MAXF (*(REG32*)(LPC_MAC_BASE + 0x014)) /* MAXimum Frame reg */
1210 #define MAC_SUPP (*(REG32*)(LPC_MAC_BASE + 0x018)) /* PHY SUPPort reg */
1211 #define MAC_TEST (*(REG32*)(LPC_MAC_BASE + 0x01C)) /* TEST reg */
1212 #define MAC_MCFG (*(REG32*)(LPC_MAC_BASE + 0x020)) /* MII Mgmt ConFiG reg */
1213 #define MAC_MCMD (*(REG32*)(LPC_MAC_BASE + 0x024)) /* MII Mgmt CoMmanD reg */
1214 #define MAC_MADR (*(REG32*)(LPC_MAC_BASE + 0x028)) /* MII Mgmt ADdRess reg */
1215 #define MAC_MWTD (*(REG32*)(LPC_MAC_BASE + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
1216 #define MAC_MRDD (*(REG32*)(LPC_MAC_BASE + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
1217 #define MAC_MIND (*(REG32*)(LPC_MAC_BASE + 0x034)) /* MII Mgmt INDicators reg (RO) */
1218 
1219 #define MAC_SA0 (*(REG32*)(LPC_MAC_BASE + 0x040)) /* Station Address 0 reg */
1220 #define MAC_SA1 (*(REG32*)(LPC_MAC_BASE + 0x044)) /* Station Address 1 reg */
1221 #define MAC_SA2 (*(REG32*)(LPC_MAC_BASE + 0x048)) /* Station Address 2 reg */
1222 
1223 #define MAC_COMMAND (*(REG32*)(LPC_MAC_BASE + 0x100)) /* Command reg */
1224 #define MAC_STATUS (*(REG32*)(LPC_MAC_BASE + 0x104)) /* Status reg (RO) */
1225 #define MAC_RXDESCRIPTOR (*(REG32*)(LPC_MAC_BASE + 0x108)) /* Rx descriptor base address reg */
1226 #define MAC_RXSTATUS (*(REG32*)(LPC_MAC_BASE + 0x10C)) /* Rx status base address reg */
1227 #define MAC_RXDESCRIPTORNUM (*(REG32*)(LPC_MAC_BASE + 0x110)) /* Rx number of descriptors reg */
1228 #define MAC_RXPRODUCEINDEX (*(REG32*)(LPC_MAC_BASE + 0x114)) /* Rx produce index reg (RO) */
1229 #define MAC_RXCONSUMEINDEX (*(REG32*)(LPC_MAC_BASE + 0x118)) /* Rx consume index reg */
1230 #define MAC_TXDESCRIPTOR (*(REG32*)(LPC_MAC_BASE + 0x11C)) /* Tx descriptor base address reg */
1231 #define MAC_TXSTATUS (*(REG32*)(LPC_MAC_BASE + 0x120)) /* Tx status base address reg */
1232 #define MAC_TXDESCRIPTORNUM (*(REG32*)(LPC_MAC_BASE + 0x124)) /* Tx number of descriptors reg */
1233 #define MAC_TXPRODUCEINDEX (*(REG32*)(LPC_MAC_BASE + 0x128)) /* Tx produce index reg */
1234 #define MAC_TXCONSUMEINDEX (*(REG32*)(LPC_MAC_BASE + 0x12C)) /* Tx consume index reg (RO) */
1235 
1236 #define MAC_TSV0 (*(REG32*)(LPC_MAC_BASE + 0x158)) /* Tx status vector 0 reg (RO) */
1237 #define MAC_TSV1 (*(REG32*)(LPC_MAC_BASE + 0x15C)) /* Tx status vector 1 reg (RO) */
1238 #define MAC_RSV (*(REG32*)(LPC_MAC_BASE + 0x160)) /* Rx status vector reg (RO) */
1239 
1240 #define MAC_FLOWCONTROLCNT (*(REG32*)(LPC_MAC_BASE + 0x170)) /* Flow control counter reg */
1241 #define MAC_FLOWCONTROLSTS (*(REG32*)(LPC_MAC_BASE + 0x174)) /* Flow control status reg */
1242 
1243 #define MAC_RXFILTERCTRL (*(REG32*)(LPC_MAC_BASE + 0x200)) /* Rx filter ctrl reg */
1244 #define MAC_RXFILTERWOLSTS (*(REG32*)(LPC_MAC_BASE + 0x204)) /* Rx filter WoL status reg (RO) */
1245 #define MAC_RXFILTERWOLCLR (*(REG32*)(LPC_MAC_BASE + 0x208)) /* Rx filter WoL clear reg (WO) */
1246 
1247 #define MAC_HASHFILTERL (*(REG32*)(LPC_MAC_BASE + 0x210)) /* Hash filter LSBs reg */
1248 #define MAC_HASHFILTERH (*(REG32*)(LPC_MAC_BASE + 0x214)) /* Hash filter MSBs reg */
1249 
1250 #define MAC_INTSTATUS (*(REG32*)(LPC_MAC_BASE + 0xFE0)) /* Interrupt status reg (RO) */
1251 #define MAC_INTENABLE (*(REG32*)(LPC_MAC_BASE + 0xFE4)) /* Interrupt enable reg */
1252 #define MAC_INTCLEAR (*(REG32*)(LPC_MAC_BASE + 0xFE8)) /* Interrupt clear reg (WO) */
1253 #define MAC_INTSET (*(REG32*)(LPC_MAC_BASE + 0xFEC)) /* Interrupt set reg (WO) */
1254 
1255 #define MAC_POWERDOWN (*(REG32*)(LPC_MAC_BASE + 0xFF4)) /* Power-down reg */
1256 #define MAC_MODULEID (*(REG32*)(LPC_MAC_BASE + 0xFFC)) /* Module ID reg (RO) */
1257 
1258 
1259 
1260 /*-------------- MultiMedia Card Interface(MCI) Controller ------------------*/
1261 #define MCI_POWER (*(REG8 *)(LPC_MCI_BASE + 0x00))
1262 #define MCI_CLOCK (*(REG16*)(LPC_MCI_BASE + 0x04))
1263 #define MCI_ARGUMENT (*(REG32*)(LPC_MCI_BASE + 0x08))
1264 #define MCI_COMMAND (*(REG16*)(LPC_MCI_BASE + 0x0C))
1265 #define MCI_RESP_CMD (*(REG8*)(LPC_MCI_BASE + 0x10))
1266 #define MCI_RESP0 (*(REG32*)(LPC_MCI_BASE + 0x14))
1267 #define MCI_RESP1 (*(REG32*)(LPC_MCI_BASE + 0x18))
1268 #define MCI_RESP2 (*(REG32*)(LPC_MCI_BASE + 0x1C))
1269 #define MCI_RESP3 (*(REG32*)(LPC_MCI_BASE + 0x20))
1270 #define MCI_DATA_TMR (*(REG32*)(LPC_MCI_BASE + 0x24))
1271 #define MCI_DATA_LEN (*(REG16*)(LPC_MCI_BASE + 0x28))
1272 #define MCI_DATA_CTRL (*(REG8*)(LPC_MCI_BASE + 0x2C))
1273 #define MCI_DATA_CNT (*(REG16*)(LPC_MCI_BASE + 0x30))
1274 #define MCI_STATUS (*(REG32*)(LPC_MCI_BASE + 0x34))
1275 #define MCI_CLEAR (*(REG16*)(LPC_MCI_BASE + 0x38))
1276 #define MCI_MASK0 (*(REG32*)(LPC_MCI_BASE + 0x3C))
1277 #define MCI_MASK1 (*(REG32*)(LPC_MCI_BASE + 0x40))
1278 #define MCI_FIFO_CNT (*(REG16*)(LPC_MCI_BASE + 0x48))
1279 #define MCI_FIFO (*(REG8*)(LPC_MCI_BASE + 0x80))
1280 
1281 /*-------------- I2S Interface Controller (I2S)----------- ------------------*/
1282 #define I2S_DAO (*(REG32*)(LPC_I2S_BASE + 0x00))
1283 #define I2S_DAI (*(REG32*)(LPC_I2S_BASE + 0x04))
1284 #define I2S_TX_FIFO (*(REG32*)(LPC_I2S_BASE + 0x08))
1285 #define I2S_RX_FIFO (*(REG32*)(LPC_I2S_BASE + 0x0C))
1286 #define I2S_STATE (*(REG32*)(LPC_I2S_BASE + 0x10))
1287 #define I2S_DMA1 (*(REG32*)(LPC_I2S_BASE + 0x14))
1288 #define I2S_DMA2 (*(REG32*)(LPC_I2S_BASE + 0x18))
1289 #define I2S_IRQ (*(REG32*)(LPC_I2S_BASE + 0x1C))
1290 #define I2S_TXRATE (*(REG32*)(LPC_I2S_BASE + 0x20))
1291 #define I2S_RXRATE (*(REG32*)(LPC_I2S_BASE + 0x24))
1292 
1293 
1294 /*-------------- General-purpose DMA Controller -----------------------------*/
1295 #define GPDMA_INT_STAT (*(REG32*)(LPC_GPDMA_BASE + 0x000))
1296 #define GPDMA_INT_TCSTAT (*(REG32*)(LPC_GPDMA_BASE + 0x004))
1297 #define GPDMA_INT_TCCLR (*(REG32*)(LPC_GPDMA_BASE + 0x008))
1298 #define GPDMA_INT_ERR_STAT (*(REG32*)(LPC_GPDMA_BASE + 0x00C))
1299 #define GPDMA_INT_ERR_CLR (*(REG32*)(LPC_GPDMA_BASE + 0x010))
1300 #define GPDMA_RAW_INT_TCSTAT (*(REG32*)(LPC_GPDMA_BASE + 0x014))
1301 #define GPDMA_RAW_INT_ERR_STAT (*(REG32*)(LPC_GPDMA_BASE + 0x018))
1302 #define GPDMA_ENABLED_CHNS (*(REG32*)(LPC_GPDMA_BASE + 0x01C))
1303 #define GPDMA_SOFT_BREQ (*(REG32*)(LPC_GPDMA_BASE + 0x020))
1304 #define GPDMA_SOFT_SREQ (*(REG32*)(LPC_GPDMA_BASE + 0x024))
1305 #define GPDMA_SOFT_LBREQ (*(REG32*)(LPC_GPDMA_BASE + 0x028))
1306 #define GPDMA_SOFT_LSREQ (*(REG32*)(LPC_GPDMA_BASE + 0x02C))
1307 #define GPDMA_CONFIG (*(REG32*)(LPC_GPDMA_BASE + 0x030))
1308 #define GPDMA_SYNC (*(REG32*)(LPC_GPDMA_BASE + 0x034))
1309 
1310 /*-------------- DMA channel 0 registers ------------------------------------*/
1311 #define GPDMA_CH0_SRC (*(REG32*)(LPC_GPDMA_BASE + 0x100))
1312 #define GPDMA_CH0_DEST (*(REG32*)(LPC_GPDMA_BASE + 0x104))
1313 #define GPDMA_CH0_LLI (*(REG32*)(LPC_GPDMA_BASE + 0x108))
1314 #define GPDMA_CH0_CTRL (*(REG32*)(LPC_GPDMA_BASE + 0x10C))
1315 #define GPDMA_CH0_CFG (*(REG32*)(LPC_GPDMA_BASE + 0x110))
1316 
1317 /*-------------- DMA channel 1 registers ------------------------------------*/
1318 #define GPDMA_CH1_SRC (*(REG32*)(LPC_GPDMA_BASE + 0x120))
1319 #define GPDMA_CH1_DEST (*(REG32*)(LPC_GPDMA_BASE + 0x124))
1320 #define GPDMA_CH1_LLI (*(REG32*)(LPC_GPDMA_BASE + 0x128))
1321 #define GPDMA_CH1_CTRL (*(REG32*)(LPC_GPDMA_BASE + 0x12C))
1322 #define GPDMA_CH1_CFG (*(REG32*)(LPC_GPDMA_BASE + 0x130))
1323 /*----------------------------------------------------------------------------*/
1324 /*-------------- CAN registers ----------------------------------------------*/
1325 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
1326 
1327 #define CAN_AFMR (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x00))
1328 #define CAN_SFF_SA (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x04))
1329 #define CAN_SFF_GRP_SA (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x08))
1330 #define CAN_EFF_SA (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x0C))
1331 #define CAN_EFF_GRP_SA (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x10))
1332 #define CAN_EOT (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x14))
1333 #define CAN_LUT_ERR_ADR (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x18))
1334 #define CAN_LUT_ERR (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x1C))
1335 #define FCANIE (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x20))
1336 #define FCANIC0 (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x24))
1337 #define FCANIC1 (*(REG32 *)(LPC_CAN_ACCEPT_BASE + 0x28))
1338 
1339 
1340 #define CAN_TX_SR (*(REG32 *)(LPC_CAN_CENTRAL_BASE + 0x00))
1341 #define CAN_RX_SR (*(REG32 *)(LPC_CAN_CENTRAL_BASE + 0x04))
1342 #define CAN_MSR (*(REG32 *)(LPC_CAN_CENTRAL_BASE + 0x08))
1343 
1344 
1345 #define CAN1MOD (*(REG32 *)(LPC_CAN1_BASE + 0x00))
1346 #define CAN1CMR (*(REG32 *)(LPC_CAN1_BASE + 0x04))
1347 #define CAN1GSR (*(REG32 *)(LPC_CAN1_BASE + 0x08))
1348 #define CAN1ICR (*(REG32 *)(LPC_CAN1_BASE + 0x0C))
1349 #define CAN1IER (*(REG32 *)(LPC_CAN1_BASE + 0x10))
1350 #define CAN1BTR (*(REG32 *)(LPC_CAN1_BASE + 0x14))
1351 #define CAN1EWL (*(REG32 *)(LPC_CAN1_BASE + 0x18))
1352 #define CAN1SR (*(REG32 *)(LPC_CAN1_BASE + 0x1C))
1353 #define CAN1RFS (*(REG32 *)(LPC_CAN1_BASE + 0x20))
1354 #define CAN1RID (*(REG32 *)(LPC_CAN1_BASE + 0x24))
1355 #define CAN1RDA (*(REG32 *)(LPC_CAN1_BASE + 0x28))
1356 #define CAN1RDB (*(REG32 *)(LPC_CAN1_BASE + 0x2C))
1357 
1358 #define CAN1TFI1 (*(REG32 *)(LPC_CAN1_BASE + 0x30))
1359 #define CAN1TID1 (*(REG32 *)(LPC_CAN1_BASE + 0x34))
1360 #define CAN1TDA1 (*(REG32 *)(LPC_CAN1_BASE + 0x38))
1361 #define CAN1TDB1 (*(REG32 *)(LPC_CAN1_BASE + 0x3C))
1362 #define CAN1TFI2 (*(REG32 *)(LPC_CAN1_BASE + 0x40))
1363 #define CAN1TID2 (*(REG32 *)(LPC_CAN1_BASE + 0x44))
1364 #define CAN1TDA2 (*(REG32 *)(LPC_CAN1_BASE + 0x48))
1365 #define CAN1TDB2 (*(REG32 *)(LPC_CAN1_BASE + 0x4C))
1366 #define CAN1TFI3 (*(REG32 *)(LPC_CAN1_BASE + 0x50))
1367 #define CAN1TID3 (*(REG32 *)(LPC_CAN1_BASE + 0x54))
1368 #define CAN1TDA3 (*(REG32 *)(LPC_CAN1_BASE + 0x58))
1369 #define CAN1TDB3 (*(REG32 *)(LPC_CAN1_BASE + 0x5C))
1370 
1371 #define CAN2MOD (*(REG32 *)(LPC_CAN2_BASE + 0x00))
1372 #define CAN2CMR (*(REG32 *)(LPC_CAN2_BASE + 0x04))
1373 #define CAN2GSR (*(REG32 *)(LPC_CAN2_BASE + 0x08))
1374 #define CAN2ICR (*(REG32 *)(LPC_CAN2_BASE + 0x0C))
1375 #define CAN2IER (*(REG32 *)(LPC_CAN2_BASE + 0x10))
1376 #define CAN2BTR (*(REG32 *)(LPC_CAN2_BASE + 0x14))
1377 #define CAN2EWL (*(REG32 *)(LPC_CAN2_BASE + 0x18))
1378 #define CAN2SR (*(REG32 *)(LPC_CAN2_BASE + 0x1C))
1379 #define CAN2RFS (*(REG32 *)(LPC_CAN2_BASE + 0x20))
1380 #define CAN2RID (*(REG32 *)(LPC_CAN2_BASE + 0x24))
1381 #define CAN2RDA (*(REG32 *)(LPC_CAN2_BASE + 0x28))
1382 #define CAN2RDB (*(REG32 *)(LPC_CAN2_BASE + 0x2C))
1383 
1384 #define CAN2TFI1 (*(REG32 *)(LPC_CAN2_BASE + 0x30))
1385 #define CAN2TID1 (*(REG32 *)(LPC_CAN2_BASE + 0x34))
1386 #define CAN2TDA1 (*(REG32 *)(LPC_CAN2_BASE + 0x38))
1387 #define CAN2TDB1 (*(REG32 *)(LPC_CAN2_BASE + 0x3C))
1388 #define CAN2TFI2 (*(REG32 *)(LPC_CAN2_BASE + 0x40))
1389 #define CAN2TID2 (*(REG32 *)(LPC_CAN2_BASE + 0x44))
1390 #define CAN2TDA2 (*(REG32 *)(LPC_CAN2_BASE + 0x48))
1391 #define CAN2TDB2 (*(REG32 *)(LPC_CAN2_BASE + 0x4C))
1392 #define CAN2TFI3 (*(REG32 *)(LPC_CAN2_BASE + 0x50))
1393 #define CAN2TID3 (*(REG32 *)(LPC_CAN2_BASE + 0x54))
1394 #define CAN2TDA3 (*(REG32 *)(LPC_CAN2_BASE + 0x58))
1395 #define CAN2TDB3 (*(REG32 *)(LPC_CAN2_BASE + 0x5C))
1396 
1397 /*----------------------------------------------------------------------------*/
1398 /*--------------- USB -------------------------------------------------------*/
1399 /*----------------------------------------------------------------------------*/
1400 /*---------------- USB Controller --------------------------------------------*/
1401 #define USB_INT_BASE 0xE01FC1C0
1402 //#define USB_BASE 0xFFE0C200 /* USB Base Address */
1403 
1404 #define USB_INT_STAT (*(REG32*)(USB_INT_BASE + 0x00))
1405 
1406 
1407 /*------ USB Device Interrupt Registers --------------------- */
1408 #define DEV_INT_STAT (*(REG32*)(USB_BASE + 0x00))
1409 #define DEV_INT_EN (*(REG32*)(USB_BASE + 0x04))
1410 #define DEV_INT_CLR (*(REG32*)(USB_BASE + 0x08))
1411 #define DEV_INT_SET (*(REG32*)(USB_BASE + 0x0C))
1412 #define DEV_INT_PRIO (*(REG32*)(USB_BASE + 0x2C))
1413 
1414 
1415 /*------ USB Device Endpoint Interrupt Registers ------------- */
1416 #define EP_INT_STAT (*(REG32*)(USB_BASE + 0x30))
1417 #define EP_INT_EN (*(REG32*)(USB_BASE + 0x34))
1418 #define EP_INT_CLR (*(REG32*)(USB_BASE + 0x38))
1419 #define EP_INT_SET (*(REG32*)(USB_BASE + 0x3C))
1420 #define EP_INT_PRIO (*(REG32*)(USB_BASE + 0x40))
1421 
1422 
1423 /*------ USB Device Endpoint Realization Registers ---------- */
1424 #define REALIZE_EP (*(REG32*)(USB_BASE + 0x44))
1425 #define EP_INDEX (*(REG32*)(USB_BASE + 0x48))
1426 #define MAXPACKET_SIZE (*(REG32*)(USB_BASE + 0x4C))
1427 
1428 
1429 /*------ USB Device Command Reagisters ---------------------- */
1430 #define CMD_CODE (*(REG32*)(USB_BASE + 0x10))
1431 #define CMD_DATA (*(REG32*)(USB_BASE + 0x14))
1432 
1433 
1434 /*------ USB Device Data Transfer Registers ----------------- */
1435 #define RX_DATA (*(REG32*)(USB_BASE + 0x18))
1436 #define TX_DATA (*(REG32*)(USB_BASE + 0x1C))
1437 #define RX_PLENGTH (*(REG32*)(USB_BASE + 0x20))
1438 #define TX_PLENGTH (*(REG32*)(USB_BASE + 0x24))
1439 #define USB_CTRL (*(REG32*)(USB_BASE + 0x28))
1440 
1441 /*------------------------ USB Device DMA Registers -----------*/
1442 #define DMA_REQ_STAT (*(REG32*)(USB_BASE + 0x50))
1443 #define DMA_REQ_CLR (*(REG32*)(USB_BASE + 0x54))
1444 #define DMA_REQ_SET (*(REG32*)(USB_BASE + 0x58))
1445 #define UDCA_HEAD (*(REG32*)(USB_BASE + 0x80))
1446 #define EP_DMA_STAT (*(REG32*)(USB_BASE + 0x84))
1447 #define EP_DMA_EN (*(REG32*)(USB_BASE + 0x88))
1448 #define EP_DMA_DIS (*(REG32*)(USB_BASE + 0x8C))
1449 #define DMA_INT_STAT (*(REG32*)(USB_BASE + 0x90))
1450 #define DMA_INT_EN (*(REG32*)(USB_BASE + 0x94))
1451 #define EOT_INT_STAT (*(REG32*)(USB_BASE + 0xA0))
1452 #define EOT_INT_CLR (*(REG32*)(USB_BASE + 0xA4))
1453 #define EOT_INT_SET (*(REG32*)(USB_BASE + 0xA8))
1454 #define NDD_REQ_INT_STAT (*(REG32*)(USB_BASE + 0xAC))
1455 #define NDD_REQ_INT_CLR (*(REG32*)(USB_BASE + 0xB0))
1456 #define NDD_REQ_INT_SET (*(REG32*)(USB_BASE + 0xB4))
1457 #define SYS_ERR_INT_STAT (*(REG32*)(USB_BASE + 0xB8))
1458 #define SYS_ERR_INT_CLR (*(REG32*)(USB_BASE + 0xBC))
1459 #define SYS_ERR_INT_SET (*(REG32*)(USB_BASE + 0xC0))
1460 
1461 /* USB Host and OTG registers are for LPC24xx only */
1462 /*------------------------ USB Host Controller -------------------------------*/
1463 #define HC_REVISION (*(REG32*)(LPC_USBHC_BASE + 0x00))
1464 #define HC_CONTROL (*(REG32*)(LPC_USBHC_BASE + 0x04))
1465 #define HC_CMD_STAT (*(REG32*)(LPC_USBHC_BASE + 0x08))
1466 #define HC_INT_STAT (*(REG32*)(LPC_USBHC_BASE + 0x0C))
1467 #define HC_INT_EN (*(REG32*)(LPC_USBHC_BASE + 0x10))
1468 #define HC_INT_DIS (*(REG32*)(LPC_USBHC_BASE + 0x14))
1469 #define HC_HCCA (*(REG32*)(LPC_USBHC_BASE + 0x18))
1470 #define HC_PERIOD_CUR_ED (*(REG32*)(LPC_USBHC_BASE + 0x1C))
1471 #define HC_CTRL_HEAD_ED (*(REG32*)(LPC_USBHC_BASE + 0x20))
1472 #define HC_CTRL_CUR_ED (*(REG32*)(LPC_USBHC_BASE + 0x24))
1473 #define HC_BULK_HEAD_ED (*(REG32*)(LPC_USBHC_BASE + 0x28))
1474 #define HC_BULK_CUR_ED (*(REG32*)(LPC_USBHC_BASE + 0x2C))
1475 #define HC_DONE_HEAD (*(REG32*)(LPC_USBHC_BASE + 0x30))
1476 #define HC_FM_INTERVAL (*(REG32*)(LPC_USBHC_BASE + 0x34))
1477 #define HC_FM_REMAINING (*(REG32*)(LPC_USBHC_BASE + 0x38))
1478 #define HC_FM_NUMBER (*(REG32*)(LPC_USBHC_BASE + 0x3C))
1479 #define HC_PERIOD_START (*(REG32*)(LPC_USBHC_BASE + 0x40))
1480 #define HC_LS_THRHLD (*(REG32*)(LPC_USBHC_BASE + 0x44))
1481 #define HC_RH_DESCA (*(REG32*)(LPC_USBHC_BASE + 0x48))
1482 #define HC_RH_DESCB (*(REG32*)(LPC_USBHC_BASE + 0x4C))
1483 #define HC_RH_STAT (*(REG32*)(LPC_USBHC_BASE + 0x50))
1484 #define HC_RH_PORT_STAT1 (*(REG32*)(LPC_USBHC_BASE + 0x54))
1485 #define HC_RH_PORT_STAT2 (*(REG32*)(LPC_USBHC_BASE + 0x58))
1486 /*------------------------ USB OTG Controller -------------------------------*/
1487 #define OTG_INT_STAT (*(REG32*)(LPC_USBOTG_BASE + 0x00))
1488 #define OTG_INT_EN (*(REG32*)(LPC_USBOTG_BASE + 0x04))
1489 #define OTG_INT_SET (*(REG32*)(LPC_USBOTG_BASE + 0x08))
1490 #define OTG_INT_CLR (*(REG32*)(LPC_USBOTG_BASE + 0x0C))
1491 /* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
1492 #define OTG_STAT_CTRL (*(REG32*)(LPC_USBOTG_BASE + 0x10))
1493 #define OTG_TIMER (*(REG32*)(LPC_USBOTG_BASE + 0x14))
1494 
1495 #define OTG_I2C_RX (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x00))
1496 #define OTG_I2C_TX (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x00))
1497 #define OTG_I2C_STS (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x04))
1498 #define OTG_I2C_CTL (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x08))
1499 #define OTG_I2C_CLKHI (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x0C))
1500 #define OTG_I2C_CLKLO (*(REG32*)(LPC_USBOTG_I2C_BASE + 0x10))
1501 
1502 /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
1503 OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
1504 #define OTG_CLK_CTRL (*(REG32*)(LPC_USBOTG_CLK_BASE + 0x04))
1505 #define OTG_CLK_STAT (*(REG32*)(LPC_USBOTG_CLK_BASE + 0x08))
1506 
1507 /* Note: below three register name convention is for LPC23xx USB device only, match
1508 with the spec. update in USB Device Section. */
1509 #define USBPortSel (*(REG32*)(LPC_USBOTG_BASE + 0x10))
1510 #define USBClkCtrl (*(REG32*)(LPC_USBOTG_CLK_BASE + 0x04))
1511 #define USBClkSt (*(REG32*)(LPC_USBOTG_CLK_BASE + 0x08))
1512 
1513 /*------------------------ External Memory Controller (EMC) LPC 22xx----------*/
1514 #if ((i_MCU_MODEL >= 2210) && (i_MCU_MODEL < 2299))
1515  // external memory controller (EMC)
1516  #define EMC_BCFG0 (*(REG32 (0xFFE00000)))
1517  #define EMC_BCFG1 (*(REG32 (0xFFE00004)))
1518  #define EMC_BCFG2 (*(REG32 (0xFFE00008)))
1519  #define EMC_BCFG3 (*(REG32 (0xFFE0000C)))
1520 #endif
1521 /*------------------------ External Memory Controller (EMC) ------------------*/
1522 #define EMC_CTRL (*(REG32 *)(LPC_EMC_BASE + 0x000))
1523 #define EMC_STAT (*(REG32 *)(LPC_EMC_BASE + 0x004))
1524 #define EMC_CONFIG (*(REG32 *)(LPC_EMC_BASE + 0x008))
1525 
1526 /*------------------------ Dynamic RAM access registers ---------------------*/
1527 #define EMC_DYN_CTRL (*(REG32 *)(LPC_EMC_BASE + 0x020))
1528 #define EMC_DYN_RFSH (*(REG32 *)(LPC_EMC_BASE + 0x024))
1529 #define EMC_DYN_RD_CFG (*(REG32 *)(LPC_EMC_BASE + 0x028))
1530 #define EMC_DYN_RP (*(REG32 *)(LPC_EMC_BASE + 0x030))
1531 #define EMC_DYN_RAS (*(REG32 *)(LPC_EMC_BASE + 0x034))
1532 #define EMC_DYN_SREX (*(REG32 *)(LPC_EMC_BASE + 0x038))
1533 #define EMC_DYN_APR (*(REG32 *)(LPC_EMC_BASE + 0x03C))
1534 #define EMC_DYN_DAL (*(REG32 *)(LPC_EMC_BASE + 0x040))
1535 #define EMC_DYN_WR (*(REG32 *)(LPC_EMC_BASE + 0x044))
1536 #define EMC_DYN_RC (*(REG32 *)(LPC_EMC_BASE + 0x048))
1537 #define EMC_DYN_RFC (*(REG32 *)(LPC_EMC_BASE + 0x04C))
1538 #define EMC_DYN_XSR (*(REG32 *)(LPC_EMC_BASE + 0x050))
1539 #define EMC_DYN_RRD (*(REG32 *)(LPC_EMC_BASE + 0x054))
1540 #define EMC_DYN_MRD (*(REG32 *)(LPC_EMC_BASE + 0x058))
1541 
1542 #define EMC_DYN_CFG0 (*(REG32 *)(LPC_EMC_BASE + 0x100))
1543 #define EMC_DYN_RASCAS0 (*(REG32 *)(LPC_EMC_BASE + 0x104))
1544 #define EMC_DYN_CFG1 (*(REG32 *)(LPC_EMC_BASE + 0x140))
1545 #define EMC_DYN_RASCAS1 (*(REG32 *)(LPC_EMC_BASE + 0x144))
1546 #define EMC_DYN_CFG2 (*(REG32 *)(LPC_EMC_BASE + 0x160))
1547 #define EMC_DYN_RASCAS2 (*(REG32 *)(LPC_EMC_BASE + 0x164))
1548 #define EMC_DYN_CFG3 (*(REG32 *)(LPC_EMC_BASE + 0x180))
1549 #define EMC_DYN_RASCAS3 (*(REG32 *)(LPC_EMC_BASE + 0x184))
1550 /*------ ТИПЫ ДАННЫХ - DATA TYPES --------------------------------------------*/
1551 /*------ СПИСОК ГЛОБАЛЬНЫХ ФУНЦИЙ - PUBLIC LIST API --------------------------*/
1552 /** @} end of group reg_addresses_LPC2000_old */
1553 /** @} end of group xgportARM7_NXP */
1554 
1555 #endif /* _ARCH_ARM_NXP_LPC2XXX_H_ */